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path: root/drivers/gpu/drm/nouveau/core/engine
AgeCommit message (Expand)AuthorFilesLines
2014-01-30drm/nouveau/disp: add a method to fetch info needed by drm vblank timestampingBen Skeggs9-7/+124
2014-01-23drm/nv50/gr: print mpc trap name when it's not an mp trapIlia Mirkin1-0/+20
2014-01-23drm/nv50/gr: update list of mp errors, make it a bitfieldIlia Mirkin1-8/+10
2014-01-23drm/nv50/gr: add more trap names to print on errorIlia Mirkin1-58/+70
2014-01-23drm/nouveau/devinit: lock/unlock crtc regs for all devices, not just pre-nv50Ilia Mirkin1-2/+7
2014-01-23drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbiosIlia Mirkin6-31/+10
2014-01-23drm/nouveau/devinit: tidy up the subdev class definitionBen Skeggs8-63/+63
2014-01-23drm/nouveau/bar: tidy up the subdev and object class definitionsBen Skeggs2-0/+2
2014-01-23drm/nouveau/instmem: tidy up the subdev class definitionBen Skeggs8-63/+63
2014-01-23drm/nve0/fifo: recover from mmu faults on bar1/bar3Ben Skeggs1-11/+20
2014-01-23drm/nve0/fifo: keep mmu fault interrupts enabled at all timesBen Skeggs1-1/+16
2014-01-23drm/nve0/fifo: update human-readable mmu fault descriptionsBen Skeggs1-11/+87
2014-01-23drm/nve0/fifo: document more intr status bitsBen Skeggs1-5/+72
2014-01-23drm/nve0/fifo: populate PBDMA status bitfield with more definitionsBen Skeggs1-2/+30
2014-01-23drm/nve0/fifo: s/subfifo/PBDMA/Ben Skeggs1-15/+15
2014-01-23drm/nve0/fifo: s/playlist/runlist/Ben Skeggs1-14/+20
2014-01-23drm/nvf0/gr: enable acceleration with our chsw ucodeBen Skeggs1-1/+1
2014-01-23drm/nv108/gr: enable acceleration with our chsw ucodeBen Skeggs1-1/+1
2014-01-23drm/nvc0-/gr: handle fwmthd interrupts in ucodeBen Skeggs7-294/+308
2014-01-23drm/nvc0-/gr: fiddle some magic around strand initBen Skeggs7-1110/+1191
2014-01-23drm/nv108/gr: initial support (need external fuc)Ben Skeggs11-10/+3071
2014-01-23drm/nv108/ce: enable copy enginesBen Skeggs1-1/+1
2014-01-23drm/nv108/fifo: initial supportBen Skeggs4-55/+113
2014-01-23drm/nvf0/gr: remove a copy+pasto in ctx reglistBen Skeggs1-1/+0
2014-01-23drm/nvc0-/gr: bring in some macros to abstract falcon isa differencesBen Skeggs12-3943/+4431
2014-01-23drm/nouveau/falcon: use vmalloc to create firwmare copiesIlia Mirkin1-5/+15
2014-01-07drm/nvce/mc: fix msi rearm on GF114Sid Boyce1-1/+1
2014-01-07drm/nvc0/gr: fix mthd data submissionKelly Doran1-1/+1
2014-01-07drm/nouveau: populate master subdev pointer only when fully constructedBen Skeggs1-0/+2
2013-12-03drm/nouveau/sw: fix oops if gpu has its display block disabledBen Skeggs1-1/+1
2013-12-03drm/nouveau/clk: Add support for NVAA/NVACRoy Spliet1-2/+2
2013-12-03drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+Roy Spliet2-0/+6
2013-11-14drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800Dan Carpenter1-1/+1
2013-11-14drm/nvc0-: remove nasty fifo swmthd hack for flip completion methodBen Skeggs2-14/+0
2013-11-14drm/nvc8/mc: msi rearm is via the nvc0 methodBen Skeggs1-1/+1
2013-11-08drm/nouveau/fb: implement various bits of work towards memory reclockingBen Skeggs1-5/+5
2013-11-08drm/nouveau/device: initial control object class, with pstate control methodsBen Skeggs3-2/+155
2013-11-08drm/nouveau/clk: implement power state and engine clock control in coreBen Skeggs2-15/+15
2013-11-08drm/nouveau/volt: implement voltage control in coreBen Skeggs4-0/+47
2013-11-08drm/nouveau/perfmon: initial infrastructure to expose performance countersBen Skeggs18-2/+1536
2013-11-08drm/nouveau/bus: add interfaces/helpers for sequencerBen Skeggs1-10/+10
2013-11-08drm/nouveau/bus: make external class definitions pointersBen Skeggs8-63/+63
2013-11-08drm/nouveau/pwr: initial implementationBen Skeggs4-0/+21
2013-11-08drm/nouveau/fifo: make external class definitions into pointersBen Skeggs16-78/+78
2013-11-08drm/nouveau/device: recognise GK208Ben Skeggs2-13/+48
2013-11-08drm/nvc0-/gr: fix a number of missing explicit array terminators...Ben Skeggs3-0/+6
2013-11-08drm/nouveau/disp: semi-complete link training sequence even if display disapp...Ben Skeggs1-16/+32
2013-11-08drm/nvd0-/disp: reorder writes to lane current control regsBen Skeggs1-4/+8
2013-11-08drm/nv94-nvc0/disp: reorder writes to lane current control regsBen Skeggs1-4/+8
2013-11-08drm/nouveau/disp: log if DP link training failsBen Skeggs1-1/+3
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