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path: root/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
AgeCommit message (Expand)AuthorFilesLines
2014-03-26drm/gf100-/gf: fix a stupid typo, waiting on wrong signal for mmctxBen Skeggs1-1/+1
2014-03-26drm/nvc0-/graph: fix gpccs fuc stack setupBen Skeggs1-197/+197
2014-01-23drm/nvc0-/gr: bring in some macros to abstract falcon isa differencesBen Skeggs1-352/+414
2013-07-05drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16Ben Skeggs1-290/+290
2013-07-05drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucodeBen Skeggs1-31/+34
2013-07-05drm/nvc0-/gr: generate cs register lists from grctx dataBen Skeggs1-316/+189
2013-07-05drm/nve0-/gr: some new gpc registers can have multiple copiesBen Skeggs1-153/+163
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs1-2/+2
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs1-26/+6
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs1-11/+66
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs1-1/+1
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs1-1/+22
2012-12-23drm/nve0/graph: fix fuc, and enable acceleration on all known chipsetsBen Skeggs1-7/+10
2012-10-03drm/nve0/gr: initial fuc implementation, based on fermi's codeBen Skeggs1-0/+530