summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/msm_kms.h
AgeCommit message (Collapse)AuthorFilesLines
2021-12-06drm/msm: Initialize MDSS irq domain at probe timeDmitry Baryshkov1-4/+4
Since commit 8f59ee9a570c ("drm/msm/dsi: Adjust probe order"), the DSI host gets initialized earlier, but this caused unability to probe the entire stack of components because they all depend on interrupts coming from the main `mdss` node (mdp5, or dpu1). To fix this issue, move mdss device initialization (which include irq domain setup) to msm_mdev_probe() time, as to make sure that the interrupt controller is available before dsi and/or other components try to initialize, finally satisfying the dependency. Fixes: 8f59ee9a570c ("drm/msm/dsi: Adjust probe order") Co-Developed-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211201202023.2313971-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-11-29drm/msm: use compatible lists to find mdp nodeKrishna Manikandan1-0/+3
In the current implementation, substring comparison using device node name is used to find mdp node during driver probe. Use compatible string list instead of node name to get mdp node from the parent mdss node. Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Changes in v2: - Use compatible lists instead of duplicate string check (Stephen Boyd) Changes in v3: - Use match tables to find the mdp node (Stephen Boyd) Changes in v4: - Drop EXPORT_SYMBOL (Dmitry Baryshkov) Link: https://lore.kernel.org/r/1636541507-5144-1-git-send-email-quic_mkrishn@quicinc.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-10-15drm/msm: Add hrtimer + kthread_work helperRob Clark1-2/+1
Before open-coding this a 2nd time, add a helper. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210927230455.1066297-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-08-17Merge tag 'drm-msm-next-2021-08-12' of ↵Dave Airlie1-3/+0
https://gitlab.freedesktop.org/drm/msm into drm-next This is the main pull for v5.15, after the early pull request with drm/scheduler conversion: * New a6xx GPU support: a680 and 7c3 * dsi: 7nm phi, sc7280 support, test pattern generator support * mdp4 fixes for older hw like the nexus7 * displayport fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs_tyanTeDGMH1X+Uf4wdyy7jYj-CinGXXVETiYOESahw@mail.gmail.com
2021-08-10drm/msm: Convert to Linux IRQ interfacesThomas Zimmermann1-1/+1
Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers don't benefit from using it. DRM IRQ callbacks are now being called directly or inlined. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Acked-by: Rob Clark <robdclark@chromium.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210803090704.32152-8-tzimmermann@suse.de
2021-08-07drm/msm/kms: drop set_encoder_mode callbackDmitry Baryshkov1-3/+0
set_encoder_mode callback is completely unused now. Drop it from msm_kms_func(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-8-dmitry.baryshkov@linaro.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: make msm_disp_state transient data structDmitry Baryshkov1-2/+4
Instead of allocating snapshotting structure at the driver probe time and later handling concurrent access, actual state, etc, make msm_disp_state transient struct. Allocate one when snapshotting happens and free it after coredump data is read by userspace. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210427001828.2375555-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: pass dump state as a function argumentDmitry Baryshkov1-1/+1
Instead of always getting the disp_state from drm device, pass it as an argument. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210427001828.2375555-2-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/disp/dpu1: add API to take DPU register snapshotAbhinav Kumar1-0/+4
Add an API to take a snapshot of DPU controller registers. This API will be used by the msm_disp_snapshot module to capture the DPU snapshot. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1618606645-19695-6-git-send-email-abhinavk@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: add support to take dpu snapshotAbhinav Kumar1-0/+3
Add the msm_disp_snapshot module which adds supports to dump dpu registers and capture the drm atomic state which can be used in case of error conditions. changes in v5: - start storing disp_state in msm_kms instead of dpu_kms - get rid of MSM_DISP_SNAPSHOT_IN_* enum by simplifying the functions - move snprintf inside the snapshot core by using varargs - get rid of some stale code comments - allow snapshot module for non-DPU targets Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1618606645-19695-3-git-send-email-abhinavk@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-02-23drm/msm/kms: Use nested locking for crtc lock instead of custom classesStephen Boyd1-6/+2
We don't need to make up custom lock classes here, we can simply use mutex_lock_nested() and pass in the index of the crtc to the locking APIs instead. This helps lockdep understand that these are really different locks while avoiding having to allocate custom lockdep classes. Cc: Krishna Manikandan <mkrishn@codeaurora.org> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Fixes: b3d91800d9ac ("drm/msm: Fix race condition in msm driver with async layer updates") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-01-31drm/msm/kms: Make a lock_class_key for each crtc mutexStephen Boyd1-2/+6
Lockdep complains about an AA deadlock when rebooting the device. base-commit: 19c329f6808995b142b3966301f217c831e7cf31 ============================================ WARNING: possible recursive locking detected 5.4.91 #1 Not tainted -------------------------------------------- reboot/5213 is trying to acquire lock: ffffff80d13391b0 (&kms->commit_lock[i]){+.+.}, at: lock_crtcs+0x60/0xa4 but task is already holding lock: ffffff80d1339110 (&kms->commit_lock[i]){+.+.}, at: lock_crtcs+0x60/0xa4 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&kms->commit_lock[i]); lock(&kms->commit_lock[i]); *** DEADLOCK *** May be due to missing lock nesting notation 6 locks held by reboot/5213: __arm64_sys_reboot+0x148/0x2a0 device_shutdown+0x10c/0x2c4 drm_atomic_helper_shutdown+0x48/0xfc modeset_lock+0x120/0x24c lock_crtcs+0x60/0xa4 stack backtrace: CPU: 4 PID: 5213 Comm: reboot Not tainted 5.4.91 #1 Hardware name: Google Pompom (rev1) with LTE (DT) Call trace: dump_backtrace+0x0/0x1dc show_stack+0x24/0x30 dump_stack+0xfc/0x1a8 __lock_acquire+0xcd0/0x22b8 lock_acquire+0x1ec/0x240 __mutex_lock_common+0xe0/0xc84 mutex_lock_nested+0x48/0x58 lock_crtcs+0x60/0xa4 msm_atomic_commit_tail+0x348/0x570 commit_tail+0xdc/0x178 drm_atomic_helper_commit+0x160/0x168 drm_atomic_commit+0x68/0x80 This is because lockdep thinks all the locks taken in lock_crtcs() are the same lock, when they actually aren't. That's because we call mutex_init() in msm_kms_init() and that assigns one static key for every lock initialized in this loop. Let's allocate a dynamic number of lock_class_keys and assign them to each lock so that lockdep can figure out an AA deadlock isn't possible here. Fixes: b3d91800d9ac ("drm/msm: Fix race condition in msm driver with async layer updates") Cc: Krishna Manikandan <mkrishn@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-01drm/msm/atomic: Convert to per-CRTC kthread_workRob Clark1-4/+13
Use a SCHED_FIFO kthread_worker for async atomic commits. We have a hard deadline if we don't want to miss a frame. Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-01drm/msm/kms: Update msm_kms_init/destroyRob Clark1-1/+7
Add msm_kms_destroy() and add err return from msm_kms_init(). Prep work for next patch. Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-01drm/msm/atomic: Drop per-CRTC locks in reverse orderRob Clark1-0/+4
lockdep dislikes seeing locks unwound in a non-nested fashion. Fixes: b3d91800d9ac ("drm/msm: Fix race condition in msm driver with async layer updates") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-11-01drm/msm: Fix race condition in msm driver with async layer updatesKrishna Manikandan1-2/+4
When there are back to back commits with async cursor update, there is a case where second commit can program the DPU hw blocks while first didn't complete flushing config to HW. Synchronize the compositions such that second commit waits until first commit flushes the composition. This change also introduces per crtc commit lock, such that commits on different crtcs are not blocked by each other. Changes in v2: - Use an array of mutexes in kms to handle commit lock per crtc. (Rob Clark) Changes in v3: - Add wrapper functions to handle lock and unlock of commit_lock for each crtc. (Rob Clark) Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-09-03drm/msm/dpu: async commit supportRob Clark1-3/+0
In addition, moving to kms->flush_commit() lets us drop the only user of kms->commit(). Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm: async commit supportRob Clark1-0/+50
Now that flush/wait/complete is decoupled from the "synchronous" part of atomic commit_tail(), add support to defer flush to a timer that expires shortly before vblank for async commits. In this way, multiple atomic commits (for example, cursor updates) can be coalesced into a single flush at the end of the frame. v2: don't hold lock over ->wait_flush(), to avoid locking interaction that was causing fps drop when combining page flips or non-async atomic commits and lots of legacy cursor updates Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm: split power control from prepare/complete_commitRob Clark1-0/+10
With atomic commit, ->prepare_commit() and ->complete_commit() may not be evenly balanced (although ->complete_commit() will complete each crtc that had been previously prepared). So these will no longer be a good place to enable/disable clocks needed for hw access. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm: add kms->flush_commit()Rob Clark1-2/+38
Add ->flush_commit(crtc_mask). Currently a no-op, but kms backends should migrate writing flush registers to this hook, so we can decouple pushing updates to hardware, and flushing the updates. Once we add async commit support, the hw updates will be pushed down to the hw synchronously, but flushing the updates will be deferred until as close to vblank as possible, so that multiple updates can be combined in a single frame. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm: convert kms->complete_commit() to crtc_maskRob Clark1-1/+1
Prep work for async commits, in which case this will be called after we no longer have the atomic state object. This drops some wait_for_vblanks(), but those should be unnecessary, as we call this after waiting for flush to complete. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm: add kms->wait_flush()Rob Clark1-3/+6
First step in re-working the atomic related internal API to prepare for async updates pending.. ->wait_flush() is intended to block until there is no in-progress flush. A crtc_mask is used, rather than an atomic state object, as this will later be used for async flush after the atomic state is destroyed. This replaces ->wait_for_crtc_commit_done() v2: update for review comments Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-12-11drm/msm: Cut dpu_kms hooks from msm_pm_suspend/resumeBruce Wang1-3/+0
Removes the traces of the non-atomic helper calls in msm_pm_suspend/resume since we just deleted those functions (see patch 1). Also removes the drm_kms_helper_poll_disable/enable calls, since the DRM_CONNECTOR_POLL_CONNECT flag is never set so periodic polling doesn't happen anyways. v2: reorganized patch order v3: made error checks less severe Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Bruce Wang <bzwang@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add SDM845 DPU supportJeykumar Sankaran1-0/+8
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add pm_suspend/resume callbacks to msm_kmsJeykumar Sankaran1-0/+3
Used by the dpu driver for custom suspend/resume. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add .commit() callback to msm_kms functionsJeykumar Sankaran1-0/+1
Called right before wait_for_commit_done() to perform kickoff for active crtcs. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/mdp5: subclass msm_mdss for mdp5Rajesh Yadav1-4/+13
SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls. This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> [seanpaul rebased on msm-next and resolved conflicts] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-06-03drm/msm: Don't subclass drm_atomic_state anymoreArchit Taneja1-14/+0
With the addition of "private_objs" in drm_atomic_state, we no longer need to subclass drm_atomic_state to store state of share resources that don't perfectly fit within planes/crtc/connector state information. We can now save this state within drm_atomic_state itself using the private objects. Remove the infrastructure that allowed subclassing of drm_atomic_state in the driver. Changes in v3: - Added to the msm atomic helper patch set Changes in v4: - None Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2018-06-03drm/msm: Add modifier to mdp_get_format argumentsJeykumar Sankaran1-1/+4
This change plumbs the new fb modifier through the various mdp/disp get_format hooks. Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul pimped out commit message a bit] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-08-02drm/msm/mdp5: Set up runtime PM for MDSSArchit Taneja1-0/+2
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and other sub-blocks. W.r.t device heirarchy, it's the parent of all these devices. The power domain of this device is actually tied to the GDSC hw. When any sub-device enables its PD, MDSS's PD is also enabled. The suspend/resume ops enable the top level clocks that end at the MDSS boundary. For now, we're letting them all be optional, since the child devices anyway hold a ref to these clocks. Until now, we'd called a runtime_get() during probe, which ensured that the GDSC was always on. Now that we've set up runtime PM for the children devices, we can get rid of this hack. Note: that the MDSS device is the platform_device in msm_drv.c. The msm_runtime_suspend/resume ops call the funcs that enable/disable the top level MDSS clocks. This is different from MDP4, where the platform device created in msm_drv.c represents MDP4 itself. It would have been nicer to hide these differences by adding new kms funcs, but runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init is called). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: remove address-space idRob Clark1-1/+0
Now that the msm_gem supports an arbitrary number of vma's, we no longer need to assign an id (index) to each address space. So rip out the associated code. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/mdp4+5: move aspace/id to base classRob Clark1-0/+4
Before we can shift to passing the address-space object to _get_iova(), we need to fix a few places (dsi+fbdev) that were hard-coding the adress space id. That gets somewhat easier if we just move these to the kms base class. Prep work for next patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-03-08drm/msm: Remove msm_debugfs_cleanup()Noralf Trønnes1-1/+0
Move the contents of msm_debugfs_cleanup() to msm_drm_uninit() to free up the drm_driver->debugfs_cleanup callback. Also remove the mdp_kms_funcs->debugfs_cleanup callback which has no users. Cc: robdclark@gmail.com Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170307204924.1002-2-noralf@tronnes.org
2017-02-06drm/msm: Set encoder's mode of operation using a kms funcArchit Taneja1-0/+3
The mdp5 kms driver currently sets up multiple encoders per interface (INTF), one for each kind of mode of operation it supports. We create 2 drm_encoders for DSI, one for Video Mode and the other for Command Mode operation. The reason behind this approach could have been that we aren't aware of the DSI device's mode of operation when we create the encoders. This makes things a bit complicated, since these encoders have to be further attached to the same DSI bridge. The easier way out is to create a single encoder, and make the DSI driver set its mode of operation when we know what the DSI device's mode flags are. Start with providing a way to set the mdp5_intf_mode using a kms func that sets the encoder's mode of operation. When constructing a DSI encoder, we set the mode of operation to Video Mode as default. When the DSI device is attached to the host, we probe the DSI mode flags and set the corresponding mode of operation. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: add debugfs to show smp block statusRob Clark1-0/+5
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: subclass drm_atomic_stateRob Clark1-0/+14
This will give the kms backends a slot to stash their own hw specific global state. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm/mdp5: Remove old kms init/destroy funcsArchit Taneja1-1/+0
With the new kms_init/destroy funcs in place for MDP5, we can get rid of the old kms funcs. Some members of the mdp5_kms struct also become redundant, so we remove those too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm/mdp5: Prepare new kms_init funcsArchit Taneja1-0/+1
With MDP5 as a new device, we need to do less for MDP when initializing modeset after all the components are bound. Create mdp5_kms_init2/destroy2 funcs that inits modeset. These will eventually replace the older kms_init/destroy funcs. In the new kms_init2, the platform_device used is the one corresponding to the new MDP5 platform_device. The new change here is that the irq is now retrieved using irq_of_parse_and_map(), since MDP5 is a child interrupt of the MDSS interrupt controller. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm/mdp5: Add MDSS top level driverArchit Taneja1-0/+2
SoCs that contain MDP5 have a top level wrapper called MDSS that manages clocks, power and irq for the sub-blocks within it. Currently, the MDSS portions are stuffed into the MDP5 driver. This makes it hard to represent the DT bindings in the correct way. We create a top level MDSS helper that handles these parts. This is essentially moving out some of the mdp5_kms irq code and MDSS register space and keeping it as a separate entity. We haven't given any clocks to the top level MDSS yet, but a AHB clock would be added in the future to access registers. One thing to note is that the resources allocated by this helper are tied to the top level platform_device (the one that allocates the drm_device struct too). This device would be the parent to MDSS sub-blocks like MDP5, DSI, eDP etc. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm: Get irq number within kms driver itselfArchit Taneja1-0/+3
The driver gets the irq number using platform_get_irq on the main kms platform device. This works fine since both MDP4 and MDP5 currently have a flat device hierarchy. The platform device tied with the drm_device points to the MDP DT node in both cases. This won't work when MDP5 supports a tree-like hierarchy. In this case, the platform device tied to the top level drm_device is the MDSS DT node, and the irq we need for KMS is the one generated by MDP5, not MDSS. Get the irq number from the MDP4/5 kms driver itself. Each driver can later provide the irq number based on what device hierarchy it uses. While we're at it, call drm_irq_install only when we have a valid KMS driver. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm: Remove unused fieldsArchit Taneja1-5/+0
These aren't used. Probably left overs when driver was refactored to support both MDP4 and MDP5. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-03-23drm/msm: fix bug after preclose removalRob Clark1-1/+0
commit 53190c7194d9a8337fe419134e44c30eb63ebd08 Author: Daniel Vetter <daniel.vetter@ffwll.ch> AuthorDate: Mon Jan 25 22:16:49 2016 +0100 Commit: Daniel Vetter <daniel.vetter@ffwll.ch> CommitDate: Mon Feb 8 09:55:50 2016 +0100 drm/msm: Nuke preclose hooks Left around the unused (and null) preclose fxn ptr, and things predictibly explode when you try to call that. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: Use customized function to wait for atomic commit doneHai Li1-0/+3
MDP FLUSH registers could indicate if the previous flush updates has taken effect at vsync boundary. Making use of this H/W feature can catch the vsync that happened between CRTC atomic_flush and *_wait_for_vblanks, to avoid unnecessary wait. This change allows kms CRTCs to use their own *_wait_for_commit_done functions to wait for FLUSH register cleared at vsync, before commit completion. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Add split display interfaceHai Li1-0/+4
This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-02-01drm/msm/mdp: add common YUV information for MDP4/MDP5Stephane Viau1-0/+2
Both MDP4 and MDP5 share some code as far as YUV support is concerned. This change adds this information and will be followed by the actual MDP4 and MDP5 YUV support patches. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-02-01drm/msm: fix fallout of atomic dpms changesRob Clark1-0/+3
As a result of atomic DPMS support, the various prepare/commit hooks get called in a way that msm dislikes. We were expecting prepare/commit to bracket a modeset, which is no longer the case. This was needed to hold various extra clk's (such as interface clks) on while we are touching registers, and in the case of mdp4 holding vblank enabled. The most straightforward way to deal with this, since we already have our own atomic_commit(), is to just handle prepare/commit internally to the driver (with some additional vfuncs for mdp4 vs mdp5), and switch everything over to instead use the new enable/disable hooks. It doesn't really change too much, despite the code motion. What used to be in the encoder/crtc dpms() fxns is split out into enable/disable. We should be able to drop our own enable-state tracking, as the atomic helpers should do this for us. But keeping that for the short term for extra debugging as atomic stablizes. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09drm/msm: add mdp5/apq8x74Rob Clark1-0/+1
Add support for the new MDP5 display controller block. The mapping between parts of the display controller and KMS is: plane -> PIPE{RGBn,VIGn} \ crtc -> LM (layer mixer) |-> MDP "device" encoder -> INTF / connector -> HDMI/DSI/eDP/etc --> other device(s) Unlike MDP4, it appears we can get by with a single encoder, rather than needing a different implementation for DTV, DSI, etc. (Ie. the register interface is same, just different bases.) Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are routed through MDP. And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from which blocks need to be allocated to the active pipes based on fetch stride. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09drm/msm: move irq utils to mdp_kmsRob Clark1-0/+11
We'll want basically the same thing for mdp5, so refactor it out so it can be shared. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09drm/msm: split out msm_kms.hRob Clark1-0/+56
Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-02 15:10:51 +0000