summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
AgeCommit message (Collapse)AuthorFilesLines
2022-09-18drm/msm/dpu: use drm_dsc_config instead of msm_display_dsc_configDmitry Baryshkov1-1/+1
There is no need to use the struct msm_display_dsc_config wrapper inside the dpu driver, use the struct drm_dsc_config directly to pass pps data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/493340/ Link: https://lore.kernel.org/r/20220711100432.455268-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2022-07-04drm/msm/dpu: Add interface support for CRC debugfsJessica Zhang1-0/+22
Add support for writing CRC values for the interface block to the debugfs by calling the necessary MISR setup/collect methods. Changes since V1: - Set values_cnt to only include phys with backing hw_intf - Loop over all drm_encs connected to crtc Changes since V2: - Remove vblank.h inclusion - Change `pos + i` to `pos + entries` - Initialize values_cnt to 0 for encoder - Change DPU_CRTC_CRC_SOURCE_INTF to DPU_CRTC_CRC_SOURCE_ENCODER (and "intf" to "enc") - Change dpu_encoder_get_num_phys to dpu_encoder_get_num_hw_intfs - Add checks for setup_misr and collect_misr in dpu_encoder_get_num_hw_intfs Changes since V3: - Remove extra whitespace - Change "enc" to "encoder" - Move crcs array to dpu_crtc_get_encoder_crc - Rename dpu_encoder_get_num_hw_intfs to dpu_encoder_get_crc_values_cnt Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/490736/ Link: https://lore.kernel.org/r/20220622171835.7558-5-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-07-04drm/msm/dpu: drop enum msm_display_capsDmitry Baryshkov1-2/+2
After the commit c46f0d69039c ("drm/msm: remove unused hotplug and edid macros from msm_drv.h") the msm_display_caps enum contains two bits describing whether the encoder should work in video or command mode. Drop the enum and replace capabilities field in struct msm_display_info with boolean is_cmd_mode field. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/485454/ Link: https://lore.kernel.org/r/20220507115942.1705872-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-05-02drm/msm/dpu: gracefully handle null fb commits for writebackAbhinav Kumar1-0/+6
kms_writeback test cases also verify with a null fb for the writeback connector job. In addition there are also other commit paths which can result in kickoffs without a valid framebuffer like while closing the fb which results in the callback to drm_atomic_helper_dirtyfb() which internally triggers a commit. Add protection in the dpu driver to ensure that commits for writeback encoders without a valid fb are gracefully skipped. changes in v2: - rename dpu_encoder_has_valid_fb to dpu_encoder_is_valid_for_commit changes in v3: - none Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/483522/ Link: https://lore.kernel.org/r/1650984096-9964-17-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-05-02drm/msm/dpu: add encoder operations to prepare/cleanup wb jobAbhinav Kumar1-0/+16
add dpu encoder APIs to prepare and cleanup writeback job for the writeback encoder. These shall be invoked from the prepare_wb_job/cleanup_wb_job hooks of the drm_writeback framework. changes in v3: - none Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/483516/ Link: https://lore.kernel.org/r/1650984096-9964-12-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-04-26drm/msm/dpu: don't use merge_3d if DSC merge topology is usedDmitry Baryshkov1-0/+6
DPU supports different topologies for the case when multiple INTFs are being driven by the single phys_enc. The driver defaults to using 3DMux in such cases. Don't use it if DSC merge is used instead. Suggested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/480922/ Link: https://lore.kernel.org/r/20220406094031.1027376-9-vkoul@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-04-26drm/msm/dsi: Pass DSC params to drm_panelVinod Koul1-0/+2
When DSC is enabled, we need to get the DSC parameters from the panel driver, so add a dsc parameter in panel to fetch and pass DSC configuration for DSI panels to DPU encoder, which will enable and then configure DSC hardware blocks accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/480910/ Link: https://lore.kernel.org/r/20220406094031.1027376-3-vkoul@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-04-26drm/msm/dpu: revise timing engine programming to support widebus featureKuogee Hsieh1-0/+2
Widebus feature will transmit two pixel data per pixel clock to interface. Timing engine provides driving force for this purpose. This patch base on HPG (Hardware Programming Guide) to revise timing engine register setting to accommodate both widebus and non widebus application. Also horizontal width parameters need to be reduced by half since two pixel data are clocked out per pixel clock when widebus feature enabled. Widebus can be enabled individually at DP. However at DSI, widebus have to be enabled along with DSC to achieve pixel clock rate be scaled down with same ratio as compression ratio when 10 bits per source component. Therefore this patch add no supports of DSI related widebus and compression. Changes in v2: -- remove compression related code from timing -- remove op_info from struct msm_drm_private -- remove unnecessary wide_bus_en variables -- pass wide_bus_en into timing configuration by struct msm_dp Changes in v3: -- split patch into 3 patches Changes in v4: -- rework timing engine to not interfere with dsi/hdmi -- cover both widebus and compression Changes in v5: -- remove supports of DSI widebus and compression Changes in v7: -- split this patch into 3 patches -- add Tested-by Changes in v8: -- move new registers writes under DATA_HCTL_EN features check. Changes in v10: -- add const inside dpu_encoder_is_widebus_enabled() -- drop useless parenthesis please Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/476281/ Link: https://lore.kernel.org/r/1645824192-29670-4-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-02-18drm/msm: move struct msm_display_info to dpu driverDmitry Baryshkov1-0/+18
The msm_display_info structure is not used by the rest of msm driver, so move it into the dpu1 (dpu_encoder.h to be precise). Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220217035358.465904-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-02-18drm/msm/dpu: get INTF blocks directly rather than through RMDmitry Baryshkov1-16/+0
INTF blocks are not really handled by resource manager, they are assigned at dpu_encoder_setup_display using dpu_encoder_get_intf(). Then this allocation is passed to RM and then returned to then dpu_encoder. So allocate them outside of RM and use them directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20220121210618.3482550-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2021-10-15drm/msm: Change dpu_crtc_get_vblank_counter to use vsync count.Mark Yacoub1-2/+2
[why] vsync_cnt atomic counter increments for every hw vsync. On the other hand, frame count is a register that increments when the frame gets actually pushed out. We cannnot read this register whenever the timing engine is off, but vblank counter should still return a valid number. This behavior also matches the downstream driver. [How] Read the encoder vsync count instead of the dpu_encoder_phys frame count. Suggested-by: Abhinav Kumar <abhinavk@codeaurora.org> CC: Rob Clark <robdclark@chromium.org> Signed-off-by: Mark Yacoub <markyacoub@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210830181359.124267-1-markyacoub@chromium.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-04-07drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu driverKalyan Thota1-0/+11
Set the flag vblank_disable_immediate = true to turn off vblank irqs immediately as soon as drm_vblank_put is requested so that there are no irqs triggered during idle state. This will reduce cpu wakeups and help in power saving. To enable vblank_disable_immediate flag the underlying KMS driver needs to support high precision vblank timestamping and also a reliable way of providing vblank counter which is incrementing at the leading edge of vblank. This patch also brings in changes to support vblank_disable_immediate requirement in dpu driver. Changes in v1: - Specify reason to add vblank timestamp support. (Rob). - Add changes to provide vblank counter from dpu driver. Changes in v2: - Fix warn stack reported by Rob Clark with v2 patch. Changes in v3: - Move back to HW frame counter (Rob). Changes in v4: - Frame count mismatch was causing a DRM WARN stack spew. DPU HW will increment the frame count at the end of the sync, where as vblank will be triggered at the fetch_start counter which is calculated as v_total - vfp. This is to start fetching early for panels with low vbp w.r.t hw latency lines. Add logic to detect the line count if it falls between vactive and v_total then return incremented frame count value. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Link: https://lore.kernel.org/r/1613651746-12783-1-git-send-email-kalyan_t@codeaurora.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-09-03drm/msm/dpu: async commit supportRob Clark1-0/+5
In addition, moving to kms->flush_commit() lets us drop the only user of kms->commit(). Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
2019-09-03drm/msm/dpu: unwind async commit handlingRob Clark1-2/+1
It attempted to avoid fps drops in the presence of cursor updates. But it is racing, and can result in hw updates after flush before vblank, which leads to underruns. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-09-03drm/msm/dpu: remove unused argRob Clark1-2/+1
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-02-05drm/msm/dpu: remove struct encoder_kickoff_paramsBruce Wang1-12/+1
The contents of struct encoder_kickoff_params are never used. Remove the structure and all remnants of it from function calls. Changes in v2 (seanpaul): - Actually remove the struct (Jeykumar) Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Bruce Wang <bzwang@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org>
2018-12-11drm/msm: dpu: Separate crtc assignment from vblank enableSean Paul1-0/+10
Instead of assigning/clearing the crtc on vblank enable/disable, we can just assign and clear the crtc on modeset. That allows us to just toggle the encoder's vblank interrupts on vblank_enable. So why is this important? Previously the driver was using the legacy pointers to assign/clear the crtc. Legacy pointers are cleared _after_ disabling the hardware, so the legacy pointer was valid during vblank_disable, but that's not something we should rely on. Instead of relying on the core ordering the legacy pointer assignments just so, we'll assign the crtc in dpu_crtc enable/disable. This is the only place that mapping can change, so we're covered there. We're also taking advantage of drm_crtc_vblank_on/off. By using this, we ensure that vblank_enable/disable can never be called while the crtc is off (which means the assigned crtc will always be valid). As such, we don't need to use modeset locks or the crtc_lock in the vblank_enable/disable routine to be sure state is consistent. ...I think. Changes in v2: - Changed crtc check in toggle_vblank to != (Jeykumar) Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [dpu_crtc.c change needed to be manually applied b/c of the dpu_crtc_reset change] Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-11drm/msm: dpu: Remove vblank_callback from encoderSean Paul1-6/+4
The indirection of registering a callback and opaque pointer isn't reall useful when there's only one callsite. So instead of having the vblank_cb registration, just give encoder a crtc and let it directly call the vblank handler. In a later patch, we'll make use of this further. Changes in v2: - None Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-11drm/msm: dpu: Move crtc runtime resume to encoderSean Paul1-2/+2
The crtc runtime resume doesn't actually operate on the crtc, but rather its encoders. The problem with this is that we need to inspect the crtc state to get the currently connected encoders. Since runtime resume isn't guaranteed to be called while holding the modeset locks (although it sometimes is), this presents a race condition. Now that we have ->enabled on the virtual encoders, and a lock to protect it, just call resume on each encoder and only restore the ones that are enabled. Changes in v2: - None Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-11drm/msm: dpu: Make legacy cursor updates asynchronousSean Paul1-2/+4
This patch sprinkles a few async/legacy_cursor_update checks through commit to ensure that cursor updates aren't blocked on vsync. There are 2 main components to this, the first is that we don't want to wait_for_commit_done in msm_atomic before returning from atomic_complete. The second is that in dpu we don't want to wait for frame_done events when updating the cursor. Changes in v2: - None Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-03drm/msm/dpu: remove RM topology definitionJeykumar Sankaran1-1/+0
RM maintained a redundant definition for display topology to identify the no. of hw blocks needed for a display and their hardware dependencies. This information can be implicitly deduced from the msm_display_topology structure available in RM reserve request. In addition to getting rid of the redundant topology, this change also removes the topology name enums and their usages. changes in v4: - remove the topology name enum entirely (Sean) changes in v5: - remove RM topology definition and their references (Sean) - Implement helper for dual mixer CRTC (Sean) changes in v6: - avoid heap memory for topology (Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-03drm/msm/dpu: remove RM dependency on connector stateJeykumar Sankaran1-3/+1
Connector states were passed around RM to update the custom topology connector property with chosen topology data. Now that we got rid of both custom properties and topology names, this change cleans up the mechanism to pass connector states across RM helpers and encoder functions. changes in v5: - Introduced in the series changes in v6: - remove parameter checking in rm reserve (Jordan) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-03drm/msm/dpu: remove display H_TILE from encoderJeykumar Sankaran1-3/+0
Encoder H_TILE values are not used for allocating the hw blocks. no. of hw_intf blocks provides the info. changes in v4: - remove irrelevant changes (Sean) - retain log macros (Sean) changes in v5: - none Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-10-03drm/msm/dpu: remove cdm block support from resource managerJeykumar Sankaran1-2/+0
Support for CDM block is not present in DPU. Remove CDM handlers from resource manager. changes in v4: - Introduced in the series changes in v5: - Remove catalog references to CDM (Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-30drm/msm/disp/dpu: Mark a handful of functions as staticJordan Crouse1-6/+0
Mark a number of static functions that are only unsed in the file that defines them and remove the prototypes from the headers where needed. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-30drm/msm/disp/dpu: Remove unused code from drm_encoder.cJordan Crouse1-8/+0
Remove dpu_encoder_check_mode and dpu_encoder_helper_hw_release frmo drm_encoder.c as they appear to be unused. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add SDM845 DPU supportJeykumar Sankaran1-0/+191
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-31 02:28:45 +0000