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path: root/drivers/gpu/drm/i915/intel_pm.c
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2022-07-12Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-4/+4
2022-07-01Merge tag 'drm-intel-gt-next-2022-06-29' of git://anongit.freedesktop.org/drm...Dave Airlie1-5/+18
2022-06-27drm/i915: Move dbuf details to INTEL_INFO->displayVille Syrjälä1-4/+4
2022-06-24Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-14/+134
2022-06-20drm: Drop drm_blend.h from drm_crtc.hVille Syrjälä1-0/+1
2022-06-17drm/i915/wm: move wm state verification to intel_pm.cJani Nikula1-9/+129
2022-05-31drm/i915/pvc: Add initial PVC workaroundsStuart Summers1-1/+15
2022-05-25Merge tag 'drm-next-2022-05-25' of git://anongit.freedesktop.org/drm/drmLinus Torvalds1-290/+255
2022-05-23Merge tag 'drm-intel-next-2022-05-20' of git://anongit.freedesktop.org/drm/dr...Tvrtko Ursulin1-5/+24
2022-05-20drm/i915/pcode: Extend pcode functions for multiple gt'sAshutosh Dixit1-5/+5
2022-05-19drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and DG2-G12Swathi Dhanavanthri1-4/+3
2022-05-04drm/i915: Fix -Wstringop-overflow warning in call to intel_read_wm_latency()Gustavo A. R. Silva1-1/+1
2022-04-20drm/i915: program wm blocks to at least blocks required per lineVinod Govindapillai1-0/+19
2022-04-06drm/i915/adlp: Fix register corruption after DDI clock enablingImre Deak1-0/+3
2022-04-01drm/i915/display: Add HAS_MBUS_JOININGJosé Roberto de Souza1-3/+3
2022-03-30drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTLJosé Roberto de Souza1-0/+52
2022-03-21drm/i915: Remove total[] and uv_total[] from ddb allocationVille Syrjälä1-60/+62
2022-03-21drm/i915: Pre-calculate plane relative data rateVille Syrjälä1-151/+36
2022-03-21drm/i915: Tweak plane ddb allocation trackingVille Syrjälä1-63/+45
2022-03-21drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä1-4/+6
2022-03-18drm/i915: Rename pre-icl SAGV enable/disable functionsVille Syrjälä1-18/+14
2022-03-18drm/i915: Reject excessive SAGV block timeVille Syrjälä1-0/+6
2022-03-18drm/i915: Probe whether SAGV works on pre-iclVille Syrjälä1-0/+14
2022-03-18drm/i915: Rework SAGV block time probingVille Syrjälä1-15/+21
2022-03-18drm/i915: Treat SAGV block time 0 as SAGV disabledVille Syrjälä1-4/+6
2022-03-09drm/i915: Remove leftover cnl SAGV block timeVille Syrjälä1-3/+0
2022-03-08drm/i915: Don't skip ddb allocation if data_rate==0Ville Syrjälä1-18/+12
2022-03-03drm/i915: Don't skip ddb allocation if data_rate==0Ville Syrjälä1-18/+12
2022-03-02drm/i915: Use str_enabled_disabled()Lucas De Marchi1-2/+2
2022-03-02drm/i915: Use str_yes_no()Lucas De Marchi1-4/+6
2022-02-28drm/i915/wm: use REG_FIELD_{PREP,GET} for PLANE_WM_BLOCKS_MASKJani Nikula1-2/+2
2022-02-24drm/i915/dg2: Tile 4 plane format supportStanislav Lisovskiy1-0/+1
2022-02-18drm/i915: Pimp icl+ sagv pre/post updateVille Syrjälä1-18/+17
2022-02-18drm/i915: Split pre-icl vs. icl+ SAGV hooks apartVille Syrjälä1-40/+74
2022-02-18drm/i915: Correctly populate use_sagv_wm for all pipesVille Syrjälä1-11/+11
2022-02-18drm/i915: Polish ilk+ wm register bitsVille Syrjälä1-29/+28
2022-02-18drm/i915: Clean up SSKPD/MLTR definesVille Syrjälä1-13/+13
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper1-0/+1
2022-02-16drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update()Ville Syrjälä1-4/+6
2022-02-16drm/i915: Use {active,scaled}_planes to compute ilk watermarksVille Syrjälä1-6/+2
2022-02-11drm/i915: Extract skl_allocate_plane_ddb()Ville Syrjälä1-17/+24
2022-02-11drm/i915: Introduce skl_plane_ddb_iterVille Syrjälä1-48/+49
2022-02-11drm/i915: Fix plane relative_data_rate calculationVille Syrjälä1-61/+2
2022-02-11drm/i915: Extract skl_ddb_entry_init()Ville Syrjälä1-19/+25
2022-02-11drm/i915: Drop pointless dev_priv argumentVille Syrjälä1-6/+5
2022-02-09drm/i915/pm: hide struct drm_i915_clock_gating_funcsJani Nikula1-0/+4
2022-02-08drm/i915: Fix mbus join config lookupVille Syrjälä1-1/+1
2022-02-08drm/i915: Fix dbuf slice config lookupVille Syrjälä1-1/+1
2022-02-07drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKLVille Syrjälä1-0/+68
2022-02-07drm/i915: Populate pipe dbuf slices more accurately during readoutVille Syrjälä1-5/+8
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