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path: root/drivers/gpu/drm/i915/intel_hdmi.c
AgeCommit message (Expand)AuthorFilesLines
2014-09-23drm/i915/hdmi: fix hdmi audio state readoutJani Nikula1-1/+1
2014-09-18drm/i915: Add limited color range readout for HDMI/DP ports on g4x/vlv/chvVille Syrjälä1-1/+6
2014-07-29Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter1-1/+1
2014-07-23drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms inSonika Jindal1-1/+1
2014-07-23drm/i915: Avoid incorrect returning for some platformsSonika Jindal1-1/+1
2014-07-23drm/i915: Add aspect ratio property for HDMIVandana Kannan1-0/+31
2014-07-09Merge tag 'drm-intel-next-2014-06-20' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-0/+65
2014-06-19drm: add register and unregister functions for connectorsThomas Wood1-1/+1
2014-06-11drm/i915/chv: Force clock buffer enablesVille Syrjälä1-0/+19
2014-06-11drm/i915/chv: Try to program the PHY used clock channel overridesVille Syrjälä1-0/+46
2014-06-04drm/i915: replace drm_get_connector_name() with direct name field useJani Nikula1-1/+1
2014-05-20drm/i915/chv: Use RMW to toggle swing calc initVille Syrjälä1-4/+14
2014-05-20drm/i915/chv: Don't do group access reads from TX lanes eitherVille Syrjälä1-11/+17
2014-05-20drm/i915/chv: Don't use PCS group access readsVille Syrjälä1-8/+24
2014-05-20drm/i915/chv: Set soft reset override bit for data lane resetsVille Syrjälä1-0/+8
2014-05-20drm/i915/chv: Reset data lanes in encoder .post_disable() hookVille Syrjälä1-0/+22
2014-05-20drm/i915/chv: Move data lane deassert to encoder pre_enableVille Syrjälä1-1/+7
2014-05-20drm/i915/chv: Fix PORT_TO_PIPE for CHVVille Syrjälä1-0/+2
2014-05-20drm/i915/chv: Fix gmbus for port DVille Syrjälä1-1/+4
2014-05-20drm/i915/chv: Configure crtc_mask correctly for CHVVille Syrjälä1-1/+8
2014-05-16drm/i915/hdmi: Remove ->mode_set callbackDaniel Vetter1-2/+5
2014-05-16drm/i915/hdmi: Remove redundant IS_VLV checksDaniel Vetter1-6/+0
2014-05-16drm/i915: Track has_audio in the pipe configDaniel Vetter1-2/+8
2014-05-16drm/i915: Track hdmi mode in the pipe configDaniel Vetter1-11/+25
2014-05-16drm/i915/hdmi: Enable hdmi mode on g4x, tooDaniel Vetter1-3/+2
2014-05-12drm/i915/chv: Pipe select change for DP and HDMIChon Ming Lee1-0/+2
2014-05-12drm/i915/chv: Add phy supports for CherryviewChon Ming Lee1-1/+83
2014-05-01Merge tag 'drm-intel-next-2014-04-16' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-6/+32
2014-04-22drm/i915: Allow user modes to exceed DVI 165MHz limitVille Syrjälä1-4/+5
2014-04-09drm/i915: move infoframe setting to after pll enable v3Jesse Barnes1-2/+16
2014-04-09drm/i915: enable HDMI mode on VLV when an HDMI sink is detectedJesse Barnes1-2/+2
2014-04-09drm/i915/vlv: disable AVI infoframe emission when writing infoframesJesse Barnes1-2/+2
2014-04-09drm/i915/vlv: write the port field in the per-pipe DIP control regJesse Barnes1-0/+12
2014-03-10drm/i915: Allow HDMI+HDMI cloning on g4xVille Syrjälä1-0/+7
2014-03-10drm/i915: Allow HDMI+VGA cloningVille Syrjälä1-1/+1
2014-03-10drm/i915: Don't use HDMI 12bpc when cloning with other encoder typesVille Syrjälä1-1/+26
2014-03-10Merge tag 'v3.14-rc6' into drm-intel-next-queuedDaniel Vetter1-3/+3
2014-03-10drm/i915: Make encoder cloning more flexibleVille Syrjälä1-1/+1
2014-03-07drm/i915: check port power domain when reading the encoder hw stateImre Deak1-0/+5
2014-03-07drm/i915: get port power domain in connector detect handlersImre Deak1-3/+26
2014-03-03drm/i915: Reject >165MHz modes w/ DVI monitorsVille Syrjälä1-3/+3
2014-02-14drm/i915: add unregister callback to connectorImre Deak1-0/+1
2014-02-13drm/i915: Convert DIP port switch cases to a simple macroVille Syrjälä1-29/+2
2014-02-05drm/i915: Reorganize display pipe register accessesAntti Koskipaa1-2/+4
2013-12-10drm/i915: Don't cast away const from infoframe bufferVille Syrjälä1-10/+10
2013-11-28drm/i915: Return a drm_mode_status enum in the mode_valid vfuncsDamien Lespiau1-2/+3
2013-11-15Merge branch 'backlight-rework' into drm-intel-next-queuedDaniel Vetter1-1/+1
2013-11-11drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centricChon Ming Lee1-4/+4
2013-11-08drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMIDamien Lespiau1-1/+1
2013-11-08drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb...Chon Ming Lee1-32/+22
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