summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2018-11-21drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak1-12/+25
2018-11-15drm/i915/bios: rename intel_aux_ch() to intel_bios_port_aux_ch()Jani Nikula1-1/+1
2018-11-09drm/i915/icl: Fix PLL mapping sanitization for DP portsImre Deak1-2/+25
2018-11-09drm/i915/ddi: Add more sanity check to the encoder HW readoutImre Deak1-24/+52
2018-11-05drm/i915/icl: Configure MG DP mode for HDMI ports tooImre Deak1-1/+67
2018-11-05drm/i915/icl: Configure MG PHY gating for HDMI ports tooImre Deak1-0/+70
2018-11-02drm/i915/icl+: Sanitize port to PLL mappingImre Deak1-0/+23
2018-11-02drm/i915: Enable AUX power for HDMI DDI/TypeC main link tooImre Deak1-3/+9
2018-11-02drm/i915: Enable AUX power earlierImre Deak1-32/+34
2018-11-02drm/i915: Use a helper to get the aux power domainImre Deak1-1/+1
2018-11-02drm/i915: Init aux_ch for HDMI ports tooImre Deak1-0/+1
2018-11-02drm/i915: Move aux_ch to intel_digital_portImre Deak1-1/+3
2018-10-31drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hookManasi Navare1-0/+49
2018-10-22drm/i915: compute_min_voltage_level sort platforms newer-to-olderRodrigo Vivi1-3/+3
2018-10-22drm/i915: ddi_clock_get sort platforms newer-to-older.Rodrigo Vivi1-8/+8
2018-10-16drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar1-3/+18
2018-10-16drm/i915/icl: create function to identify combophy portMahesh Kumar1-7/+8
2018-10-15drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCONShashank Sharma1-0/+7
2018-10-15drm/i915: Add AVI infoframe support for LSPCONShashank Sharma1-4/+15
2018-10-15drm/i915: Add CRTC output format YCBCR 4:2:0Shashank Sharma1-1/+1
2018-10-05drm/i915: Apply correct ddi translation table for AML deviceLee, Shawn C1-3/+3
2018-10-05drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_selMaarten Lankhorst1-7/+8
2018-10-01drm/i915: Pass intel_encoder to infoframe functionsVille Syrjälä1-3/+3
2018-09-25drm/i915: use for_each_pipe loop to assign crtc_maskMahesh Kumar1-1/+3
2018-09-18drm/i915/psr: Enable AUX-A IO power well on ICL for PSRDhinakaran Pandiyan1-1/+1
2018-09-04drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä1-1/+1
2018-09-01drm/i915/dp_mst: Fix enabling pipe clock for all streamsImre Deak1-8/+9
2018-08-20drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLLManasi Navare1-2/+79
2018-08-14drm/i915: set DP Main Stream Attribute for color range on DDI platformsJani Nikula1-0/+4
2018-07-25drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni1-0/+3
2018-07-25drm/i915/icl: program MG_DP_MODEPaulo Zanoni1-0/+2
2018-07-24drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDIManasi Navare1-6/+129
2018-07-13drm/i915: Nuke dev_priv->irq_port[]Ville Syrjälä1-1/+0
2018-07-13drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.Clint Taylor1-2/+11
2018-07-06drm/i915/ddi: Simplify get_encoder_power_domains()Imre Deak1-12/+7
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+1
2018-06-26drm/i915/ddi: Get AUX power domain for DP main link tooImre Deak1-4/+50
2018-06-15drm/i915/icl: implement DVFS for ICLPaulo Zanoni1-0/+2
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni1-0/+16
2018-06-14drm/i915/ddi: Set HDMI infoframes with pipe clocks enabledImre Deak1-5/+5
2018-06-14drm/i915/ddi: Push pipe clock enabling to encodersImre Deak1-0/+8
2018-06-12drm/i915/icl: Add DDI HDMI level selection for ICLManasi Navare1-1/+8
2018-06-01drm/i915/icl: Calculate link clock using the new registersArkadiusz Hiler1-2/+7
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare1-0/+26
2018-06-01drm/i915/icl: fix icl_unmap/map_plls_to_portsMahesh Kumar1-2/+4
2018-05-23drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi codeVille Syrjälä1-29/+0
2018-05-18drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+Ville Syrjälä1-0/+20
2018-05-07drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni1-4/+94
2018-04-30drm/i915/icl: Fix the DP Max Voltage for ICLManasi Navare1-1/+7
2018-04-30drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDIManasi Navare1-3/+188
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 23:24:27 +0000