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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2021-03-24drm/i915: reserve stolen for LMEM regionCQ Tang1-0/+2
2021-03-12drm/i915: Workaround async flip + VT-d corruption on HSW/BDWVille Syrjälä1-1/+22
2021-03-11Merge drm/drm-next into drm-intel-nextJani Nikula1-0/+7
2021-02-22drm/i915/reg: add stream splitter configuration definitionsJani Nikula1-0/+3
2021-02-08drm/i915: Disable atomics in L3 for gen9Chris Wilson1-0/+7
2021-02-02Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.or...Jani Nikula1-4/+46
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä1-0/+2
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä1-0/+1
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup1-1/+22
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup1-2/+20
2021-01-26drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa1-1/+4
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä1-7/+7
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada1-0/+9
2021-01-13drm/i915/hdcp: Add HDCP 2.2 stream registerAnshuman Gupta1-0/+39
2021-01-13drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta1-0/+1
2021-01-11drm/i915: Fix HTI port checkingJosé Roberto de Souza1-2/+1
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter1-2/+5
2020-12-03drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register defManasi Navare1-0/+1
2020-12-03Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org...Dave Airlie1-0/+26
2020-12-02drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()Jani Nikula1-2/+4
2020-11-19drm/i915/perf: workaround register corruption in OATAILPTRLionel Landwerlin1-0/+2
2020-11-13Merge tag 'drm-intel-gt-next-2020-11-12-1' of git://anongit.freedesktop.org/d...Dave Airlie1-7/+5
2020-11-11drm/i915/tgl: Fix Media power gate sequence.Rodrigo Vivi1-7/+5
2020-11-09drm/i915/dg1: map/unmap pll clocksLucas De Marchi1-0/+24
2020-10-30drm/i915: Enable hpd logic only for ports that are presentVille Syrjälä1-17/+0
2020-10-30drm/i915: Remove per-platform IIR HPD maskingVille Syrjälä1-12/+3
2020-10-30drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bitsVille Syrjälä1-20/+20
2020-10-30drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()Ville Syrjälä1-18/+19
2020-10-30drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bitsVille Syrjälä1-25/+25
2020-10-30drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()Ville Syrjälä1-5/+5
2020-10-30drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pinVille Syrjälä1-6/+6
2020-10-30drm/i915: s/PORT_TC/TC_PORT_/Ville Syrjälä1-30/+30
2020-10-29drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registersVille Syrjälä1-4/+5
2020-10-23drm/i915/dg1: invert HPD pinsClinton A Taylor1-0/+4
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi1-0/+8
2020-10-21drm/i915: Introduce scaling filter related registers and bit fieldsPankaj Bharadiya1-0/+22
2020-10-20drm/i915: Sort the mess around ICP TC hotplugs regsVille Syrjälä1-107/+106
2020-10-19drm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza1-5/+9
2020-10-15drm/i915/dg1: Update DMC_DEBUG registerAnshuman Gupta1-0/+1
2020-10-15drm/i915/dg1: Add initial DG1 workaroundsStuart Summers1-5/+9
2020-10-15drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi1-0/+4
2020-10-15drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup1-1/+16
2020-10-09drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GTMatt Roper1-2/+2
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak1-0/+1
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper1-0/+3
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä1-0/+3
2020-09-28drm/i915: Relocate CHV CGM gamma masksVille Syrjälä1-3/+6
2020-09-28drm/i915: Add support for async flips in I915Karthik B S1-0/+1
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä1-24/+12
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä1-1/+0
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