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path: root/drivers/gpu/drm/i915/i915_reg.h
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2021-08-12Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/d...Dave Airlie1-1/+47
2021-08-05drm/i915/dg2: Add SQIDI steeringMatt Roper1-0/+2
2021-08-05drm/i915/xehp: handle new steering optionsDaniele Ceraolo Spurio1-0/+3
2021-08-03drm/i915/xehp: Changes to ss/eu definitionsMatthew Auld1-0/+3
2021-08-03drm/i915/guc/slpc: Sysfs hooks for SLPCVinay Belgaumkar1-0/+2
2021-08-03drm/i915/guc/slpc: Cache platform frequency limitsVinay Belgaumkar1-0/+3
2021-07-27drm/i915/guc: Provide mmio list to be saved/restored on engine resetJohn Harrison1-0/+1
2021-07-26drm/i915/gt: nuke gen6_hw_idLucas De Marchi1-1/+10
2021-07-24drm/i915/xehp: Extra media engines - Part 3 (reset)John Harrison1-0/+8
2021-07-24drm/i915/xehp: Extra media engines - Part 2 (interrupts)John Harrison1-0/+3
2021-07-24drm/i915/xehp: Extra media engines - Part 1 (engine definitions)John Harrison1-0/+6
2021-07-22drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_idLucas De Marchi1-1/+1
2021-07-22drm/i915/guc: Implement GuC context operations for new intefaceMatthew Brost1-0/+1
2021-07-22drm/i915/xehp: Handle new device context ID formatStuart Summers1-0/+5
2021-07-06drm/i915/display/dg1: Correctly map DPLLs during state readoutJosé Roberto de Souza1-3/+0
2021-07-01drm/i915/display/dg1: Correctly map DPLLs during state readoutJosé Roberto de Souza1-3/+0
2021-07-01Merge drm/drm-next into drm-intel-nextJani Nikula1-2/+15
2021-06-24drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanlineJosé Roberto de Souza1-0/+1
2021-06-24drm/i915/display/adl_p: Implement Wa_16011168373José Roberto de Souza1-0/+8
2021-06-24drm/i915/display/adl_p: Implement Wa_22012278275José Roberto de Souza1-2/+4
2021-06-21drm/i915/xelpd: Pipe A DMC pluggingAnusha Srivatsa1-1/+1
2021-06-16drm/i915/jsl: Add W/A 1409054076 for JSLTejas Upadhyay1-0/+1
2021-06-10Merge tag 'drm-intel-next-2021-06-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-48/+152
2021-06-09drm/i915/adl_p: CDCLK crawl support for ADLStanislav Lisovskiy1-0/+2
2021-06-07drm/i915: Add remaining conversions to GRAPHICS_VERLucas De Marchi1-13/+13
2021-06-02Merge tag 'drm-intel-gt-next-2021-05-28' of git://anongit.freedesktop.org/drm...Dave Airlie1-2/+15
2021-05-27drm/i915: Add Wa_14010733141Aditya Swarup1-0/+6
2021-05-27drm/i915/adl_p: Implement Wa_22012358565Ville Syrjälä1-0/+8
2021-05-27drm/i915/adl_p: Disable FIFO underrun recoveryVille Syrjälä1-0/+1
2021-05-26drm/i915/xelpd: Add VRR guardband for VRR CTLManasi Navare1-0/+2
2021-05-26drm/i915/xelpd: Enhanced pipe underrun reportingMatt Roper1-0/+9
2021-05-19drm/i915/adlp: Add PIPE_MISC2 programmingAnusha Srivatsa1-0/+7
2021-05-19drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTLImre Deak1-0/+1
2021-05-19drm/i915/adl_p: Add PLL SupportAnusha Srivatsa1-0/+8
2021-05-19drm/i915/adl_p: Tx escape clock with DSIMika Kahola1-0/+6
2021-05-19drm/i915/adl_p: MBUS programmingVandita Kulkarni1-0/+11
2021-05-19drm/i915/adl_p: Add ddb allocation supportVandita Kulkarni1-4/+18
2021-05-19drm/i915/adl_p: Implement TC sequencesJosé Roberto de Souza1-0/+10
2021-05-19drm/i915/adl_p: Add dedicated SAGV watermarksMatt Roper1-17/+42
2021-05-19drm/i915/dmc: Rename macro names containing csrAnusha Srivatsa1-14/+14
2021-05-14drm/i915/adl_p: Implement Wa_22011091694José Roberto de Souza1-0/+3
2021-05-14drm/i915/bigjoiner: atomic commit changes for uncompressed joinerAnimesh Manna1-0/+2
2021-05-14drm/i915/adl_p: Enable/disable loadgen sharingMika Kahola1-0/+1
2021-05-14drm/i915/adl_p: Extend PLANE_WM bits for blocks & linesMatt Roper1-2/+2
2021-05-14drm/i915/xelpd: Increase maximum watermark lines to 255Matt Roper1-2/+1
2021-05-12drm/i915/xelpd: Add Wa_14011503030Matt Roper1-0/+2
2021-05-12drm/i915/xelpd: Add XE_LPD power wellsMatt Roper1-0/+10
2021-05-12drm/i915/xelpd: Handle proper AUX interrupt bitsMatt Roper1-9/+11
2021-05-07drm/i915/xelpd: Support 128k plane strideJuha-Pekka Heikkilä1-0/+2
2021-04-26drm/i915: Give C0DRB3/C1DRB3 a _BW suffixVille Syrjälä1-2/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-05 19:36:32 +0000