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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2013-03-26drm/i915: HSW PM Frequency bits fixRodrigo Vivi1-0/+1
2013-03-23drm/i915: Implement WaSwitchSolVfFArbitrationPriorityBen Widawsky1-0/+1
2013-03-23drm/i915: DSPFW and BLC regs are in the display offset rangeJesse Barnes1-3/+5
2013-03-23drm/i915: add media well to VLV force wake routines v2Jesse Barnes1-0/+2
2013-03-19Merge tag 'v3.9-rc3' into drm-intel-next-queuedDaniel Vetter1-2/+2
2013-03-19drm/i915: allow force wake at init time on VLV v2Jesse Barnes1-0/+2
2013-03-06drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bitsPatrik Jakobsson1-2/+2
2013-03-04drm/i915: rename some HDMI bit definitionsPaulo Zanoni1-3/+3
2013-03-04drm/i915: remove duplicated SDVO/HDMI bit definitionsPaulo Zanoni1-11/+6
2013-03-04drm/i915: unify the definitions of the HDMI/SDVO registerPaulo Zanoni1-56/+55
2013-03-04drm/i915: clarify confusion between SDVO and HDMI registersPaulo Zanoni1-10/+9
2013-03-03drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipeRodrigo Vivi1-8/+10
2013-02-20drm/i915: Refactor gen2 to gen4 vblank interrupt handlingVille Syrjälä1-0/+1
2013-02-20drm/i915: use FPGA_DBG for the "unclaimed register" checksPaulo Zanoni1-0/+3
2013-02-20drm/i915: Implement pipe CSC based limited range RGB outputVille Syrjälä1-1/+51
2013-02-20drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+Ville Syrjälä1-0/+1
2013-02-20drm/i915: Preserve the DDI link reversal configurationDamien Lespiau1-0/+1
2013-02-20drm/i915: Preserve the FDI line reversal override bit on CPTDamien Lespiau1-1/+1
2013-02-20drm/i915: detect wrong MCH watermark valuesDaniel Vetter1-0/+4
2013-02-15drm/i915: unify HDMI/DP hpd definitionsDaniel Vetter1-19/+9
2013-02-14drm/i915: Fix RC6VIDS encode/decodeBen Widawsky1-2/+2
2013-02-08Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...Dave Airlie1-0/+3
2013-01-31drm/i915: Introduce i915_vgacntrl_reg()Ville Syrjälä1-0/+2
2013-01-31drm/i915: Fix CAGF for HSWBen Widawsky1-0/+2
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky1-0/+1
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni1-4/+4
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä1-13/+13
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä1-2/+8
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä1-4/+4
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä1-4/+6
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä1-5/+5
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä1-1/+1
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä1-1/+1
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-24drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-24drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä1-2/+2
2013-01-24drm/i915: DSPFW registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-24drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä1-2/+2
2013-01-24drm/i915: Cursor registers need an offset on VLVVille Syrjälä1-6/+6
2013-01-24drm/i915: Pipe registers need an offset on VLVVille Syrjälä1-10/+10
2013-01-24drm/i915: Primary plane registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-24drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä1-16/+16
2013-01-24drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä1-6/+6
2013-01-24drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä1-11/+11
2013-01-24drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä1-1/+1
2013-01-23drm/i915: Disable AsyncFlip performance optimisationsChris Wilson1-0/+1
2013-01-20drm/i915: Fix RGB color range property for PCH platformsVille Syrjälä1-0/+1
2013-01-17drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLVVille Syrjälä1-2/+2
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