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drivers
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drm
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i915
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i915_reg.h
Age
Commit message (
Expand
)
Author
Files
Lines
2013-03-26
drm/i915: HSW PM Frequency bits fix
Rodrigo Vivi
1
-0
/
+1
2013-03-23
drm/i915: Implement WaSwitchSolVfFArbitrationPriority
Ben Widawsky
1
-0
/
+1
2013-03-23
drm/i915: DSPFW and BLC regs are in the display offset range
Jesse Barnes
1
-3
/
+5
2013-03-23
drm/i915: add media well to VLV force wake routines v2
Jesse Barnes
1
-0
/
+2
2013-03-19
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Daniel Vetter
1
-2
/
+2
2013-03-19
drm/i915: allow force wake at init time on VLV v2
Jesse Barnes
1
-0
/
+2
2013-03-06
drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits
Patrik Jakobsson
1
-2
/
+2
2013-03-04
drm/i915: rename some HDMI bit definitions
Paulo Zanoni
1
-3
/
+3
2013-03-04
drm/i915: remove duplicated SDVO/HDMI bit definitions
Paulo Zanoni
1
-11
/
+6
2013-03-04
drm/i915: unify the definitions of the HDMI/SDVO register
Paulo Zanoni
1
-56
/
+55
2013-03-04
drm/i915: clarify confusion between SDVO and HDMI registers
Paulo Zanoni
1
-10
/
+9
2013-03-03
drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe
Rodrigo Vivi
1
-8
/
+10
2013-02-20
drm/i915: Refactor gen2 to gen4 vblank interrupt handling
Ville Syrjälä
1
-0
/
+1
2013-02-20
drm/i915: use FPGA_DBG for the "unclaimed register" checks
Paulo Zanoni
1
-0
/
+3
2013-02-20
drm/i915: Implement pipe CSC based limited range RGB output
Ville Syrjälä
1
-1
/
+51
2013-02-20
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
Ville Syrjälä
1
-0
/
+1
2013-02-20
drm/i915: Preserve the DDI link reversal configuration
Damien Lespiau
1
-0
/
+1
2013-02-20
drm/i915: Preserve the FDI line reversal override bit on CPT
Damien Lespiau
1
-1
/
+1
2013-02-20
drm/i915: detect wrong MCH watermark values
Daniel Vetter
1
-0
/
+4
2013-02-15
drm/i915: unify HDMI/DP hpd definitions
Daniel Vetter
1
-19
/
+9
2013-02-14
drm/i915: Fix RC6VIDS encode/decode
Ben Widawsky
1
-2
/
+2
2013-02-08
Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...
Dave Airlie
1
-0
/
+3
2013-01-31
drm/i915: Introduce i915_vgacntrl_reg()
Ville Syrjälä
1
-0
/
+2
2013-01-31
drm/i915: Fix CAGF for HSW
Ben Widawsky
1
-0
/
+2
2013-01-28
drm/i915: Implement WaVSRefCountFullforceMissDisable
Ben Widawsky
1
-0
/
+1
2013-01-26
drm/i915: fix intel_init_power_wells
Paulo Zanoni
1
-4
/
+4
2013-01-26
drm/i915: SWF screatch registers need an offset on VLV
Ville Syrjälä
1
-13
/
+13
2013-01-26
drm/i915: Include display_mmio_offset in sequencer index/data registers
Ville Syrjälä
1
-2
/
+8
2013-01-26
drm/i915: PLL registers need an offset on VLV
Ville Syrjälä
1
-4
/
+4
2013-01-24
drm/i915: DPIO registers are VLV only and need an offset
Ville Syrjälä
1
-4
/
+6
2013-01-24
drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
Ville Syrjälä
1
-5
/
+5
2013-01-24
drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
Ville Syrjälä
1
-1
/
+1
2013-01-24
drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
Ville Syrjälä
1
-1
/
+1
2013-01-24
drm/i915: Pipe palette registers need an offset on VLV
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Pipe timing registers need an offset on VLV
Ville Syrjälä
1
-18
/
+18
2013-01-24
drm/i915: PORT_HOTPLUG registers need an offset on VLV
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Panel fitter registers need an offset on VLV
Ville Syrjälä
1
-3
/
+3
2013-01-24
drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: DSPFW registers need an offset on VLV
Ville Syrjälä
1
-3
/
+3
2013-01-24
drm/i915: VLV_DDL is VLV only and needs an offset
Ville Syrjälä
1
-2
/
+2
2013-01-24
drm/i915: Cursor registers need an offset on VLV
Ville Syrjälä
1
-6
/
+6
2013-01-24
drm/i915: Pipe registers need an offset on VLV
Ville Syrjälä
1
-10
/
+10
2013-01-24
drm/i915: Primary plane registers need an offset on VLV
Ville Syrjälä
1
-18
/
+18
2013-01-24
drm/i915: PIPE M/N registers need an offset on VLV
Ville Syrjälä
1
-16
/
+16
2013-01-24
drm/i915: VLV_VIDEO_DIP_CTL is for VLV only
Ville Syrjälä
1
-6
/
+6
2013-01-24
drm/i915: Per-pipe PP registers are for VLV only
Ville Syrjälä
1
-11
/
+11
2013-01-24
drm/i915: AUD_VID_DID needs an offset on VLV
Ville Syrjälä
1
-1
/
+1
2013-01-23
drm/i915: Disable AsyncFlip performance optimisations
Chris Wilson
1
-0
/
+1
2013-01-20
drm/i915: Fix RGB color range property for PCH platforms
Ville Syrjälä
1
-0
/
+1
2013-01-17
drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLV
Ville Syrjälä
1
-2
/
+2
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