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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.c
AgeCommit message (Expand)AuthorFilesLines
2021-10-04drm/i915: Pass the lane to intel_ddi_level()Ville Syrjälä1-1/+1
2021-10-04drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()Ville Syrjälä1-2/+0
2021-10-04drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä1-3/+4
2021-09-30drm/i915: s/ddi_translations/trans/Ville Syrjälä1-6/+6
2021-08-30drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna1-0/+147
2021-08-26drm/i915/snps: constify struct intel_mpllb_state arrays harderJani Nikula1-7/+7
2021-08-13drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula1-44/+17
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun1-0/+14
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper1-0/+15
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper1-0/+54
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper1-12/+274
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper1-0/+517