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path:
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drivers
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gpu
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drm
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i915
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display
/
intel_dpll_mgr.c
Age
Commit message (
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Author
Files
Lines
2019-10-29
drm/i915: Fix PCH reference clock for FDI on HSW/BDW
Ville Syrjälä
1
-0
/
+15
2019-08-16
drm/i915: Wrappers for display register waits
Daniele Ceraolo Spurio
1
-33
/
+11
2019-08-07
drm/i915: rename intel_drv.h to display/intel_display_types.h
Jani Nikula
1
-1
/
+1
2019-07-18
drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
Vivek Kasireddy
1
-4
/
+14
2019-07-11
drm/i915/tgl: Update DPLL clock reference register
José Roberto de Souza
1
-2
/
+6
2019-07-11
drm/i915/tgl: Add DPLL registers
Lucas De Marchi
1
-5
/
+19
2019-07-11
drm/i915/tgl: Add pll manager
Vandita Kulkarni
1
-1
/
+18
2019-07-11
drm/i915: Polish intel_shared_dpll_swap_state()
Ville Syrjälä
1
-12
/
+7
2019-07-10
drm/i915: Transition port type checks to phy checks
Matt Roper
1
-5
/
+6
2019-07-09
drm/i915/icl: Clear the shared port PLLs from the new crtc state
Imre Deak
1
-5
/
+7
2019-07-09
drm/i915: Clear the shared PLL from the put_dplls() hook
Imre Deak
1
-6
/
+14
2019-07-05
drm/i915/ehl: Add support for DPLL4 (v10)
Vivek Kasireddy
1
-4
/
+43
2019-07-03
drm/i915/display: Handle lost primary_port across suspend
Chris Wilson
1
-9
/
+4
2019-07-01
drm/i915: Keep the TypeC port mode fixed when the port is active
Imre Deak
1
-1
/
+27
2019-07-01
drm/i915/icl: Reserve all required PLLs for TypeC ports
Imre Deak
1
-41
/
+112
2019-07-01
drm/i915/icl: Split getting the DPLLs to port type specific functions
Imre Deak
1
-34
/
+66
2019-07-01
drm/i915: Sanitize the shared DPLL find/reference interface
Imre Deak
1
-37
/
+70
2019-07-01
drm/i915: Sanitize the shared DPLL reserve/release interface
Imre Deak
1
-82
/
+139
2019-07-01
drm/i915: Sanitize the terminology used for TypeC port modes
Imre Deak
1
-1
/
+1
2019-06-17
drm/i915: move modesetting core code under display/
Jani Nikula
1
-0
/
+3359