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path: root/drivers/gpu/drm/i915/display/intel_display_power.c
AgeCommit message (Expand)AuthorFilesLines
2020-11-17drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platformsBob Paauwe1-2/+11
2020-11-12drm/i915/display: Make get_allowed_dc_mask().max_dc set a chain of if and elsesJosé Roberto de Souza1-11/+7
2020-11-12drm/i915/display: Group DC9 mask setJosé Roberto de Souza1-10/+8
2020-10-20drm/i915: Reorder hpd init vs. display resumeVille Syrjälä1-1/+2
2020-10-19drm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza1-0/+14
2020-10-15drm/i915/dg1: DG1 does not support DC6Anshuman Gupta1-1/+4
2020-10-15drm/i915/dg1: Add initial DG1 workaroundsStuart Summers1-2/+3
2020-10-15drm/i915/dg1: Add DG1 power wellsLucas De Marchi1-2/+5
2020-10-15drm/i915/cnl: skip PW_DDI_F on certain skusLucas De Marchi1-12/+7
2020-10-15drm/i915/display: allow to skip certain power wellsAditya Swarup1-6/+18
2020-08-28drm/i915/tgl: Fix stepping WA matchingJosé Roberto de Souza1-1/+1
2020-08-17drm/i915/tgl: Fix TC-cold block/unblock sequenceImre Deak1-5/+5
2020-08-17drm/i915/tgl: Make sure TC-cold is blocked before enabling TC AUX power wellsImre Deak1-6/+6
2020-08-17drm/i915: Update bw_buddy pagemask tableMatt Roper1-1/+1
2020-08-17drm/i915: Implement WA 14011294188José Roberto de Souza1-0/+6
2020-07-02drm/i915/display: prefer dig_port to reference intel_digital_portLucas De Marchi1-2/+2
2020-06-26drm/i915/gen12: implement Wa_14011508470Matt Atwood1-0/+8
2020-06-22drm/i915/params: switch to device specific parametersJani Nikula1-7/+7
2020-06-09drm/i915/rkl: RKL uses ABOX0 for pixel transfersMatt Roper1-25/+30
2020-05-20drm/i915/rkl: Add power well supportMatt Roper1-1/+184
2020-05-19drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-11/+24
2020-05-16drm/i915: Introduce proper dbuf stateVille Syrjälä1-4/+4
2020-05-16drm/i915: Unify the low level dbuf codeVille Syrjälä1-25/+19
2020-05-16drm/i915: Polish some dbuf debugsVille Syrjälä1-19/+17
2020-04-23drm/i915/icl: Fix timeout handling during TypeC AUX power well enablingImre Deak1-49/+25
2020-04-21drm/i915: drop a bunch of superfluous inlinesJani Nikula1-3/+2
2020-04-20drm/i915: Use single set of AUX powerwell ops for gen11+Matt Roper1-182/+62
2020-04-18drm/i915: Add ICL PG3 PW ID for EHLAnshuman Gupta1-1/+1
2020-04-17drm/i915/tc: Do not warn when aux power well of static TC ports timeoutJosé Roberto de Souza1-17/+42
2020-04-17drm/i915/tc/tgl: Implement TC cold sequencesJosé Roberto de Souza1-0/+108
2020-04-17drm/i915/tc: Skip ref held check for TC legacy aux power wellsJosé Roberto de Souza1-0/+3
2020-04-17drm/i915/tc/icl: Implement TC cold sequencesJosé Roberto de Souza1-1/+24
2020-04-17drm/i915/display: Split hsw_power_well_enable() into twoJosé Roberto de Souza1-7/+32
2020-04-17drm/i915/display: Move out code to return the digital_port of the aux chJosé Roberto de Souza1-32/+37
2020-04-17drm/i915: Power well id for ICL PG3Anshuman Gupta1-3/+3
2020-04-16drm/i915/tgl: TBT AUX should use TC power well opsMatt Roper1-6/+6
2020-04-15drm/i915/tgl: Extend Wa_1409767108:tgl to B0 steppingMatt Roper1-1/+1
2020-03-25drm/i915/display_power: use struct drm_device based loggingJani Nikula1-7/+15
2020-02-26drm/i915/tgl: Allow DC5/DC6 entry while PG2 is activeMatt Roper1-6/+12
2020-02-23drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is availablePankaj Bharadiya1-76/+105
2020-02-21drm/i915/tgl: Add Wa_22010178259:tglMatt Roper1-0/+8
2020-02-20drm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display initMatt Roper1-0/+4
2020-02-20drm/i915: Program MBUS with rmw during initializationMatt Roper1-5/+9
2020-02-19drm/i915: Read rawclk_freq earlierChris Wilson1-6/+3
2020-02-15drm/i915: Ensure no conflicts with BIOS when updating DbufStanislav Lisovskiy1-2/+4
2020-02-05drm/i915: Manipulate DBuf slices properlyStanislav Lisovskiy1-64/+38
2020-02-05drm/i915: Introduce parameterized DBUF_CTLStanislav Lisovskiy1-19/+21
2020-02-05drm/i915: Remove skl_ddl_allocation structStanislav Lisovskiy1-4/+4
2020-02-04drm/i915/display: Defer application of initial chv_phy_controlChris Wilson1-4/+10
2020-01-31drm/i915: s/init_cdclk/init_cdclk_hw/Ville Syrjälä1-8/+8
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