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path: root/drivers/gpu/drm/i915/display/intel_display.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-08drm/i915: Fix the async flip wm0/ddb optimizationVille Syrjälä1-16/+22
2022-03-08drm/i915: Check async flip capability early onVille Syrjälä1-7/+72
2022-03-08drm/i915: Avoid negative shift due to bigjoiner_pipes==0Ville Syrjälä1-1/+4
2022-02-23Merge tag 'drm-intel-gt-next-2022-02-17' of git://anongit.freedesktop.org/drm...Rodrigo Vivi1-1/+1
2022-02-23drm/i915: Properly clear crtc state when disabling it fully, againVille Syrjälä1-3/+5
2022-02-23drm/i915: Remove odd any_ms=true assignmentVille Syrjälä1-3/+1
2022-02-21drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.hJani Nikula1-1/+2
2022-02-18drm/i915/dg2: Enable 5th portMatt Roper1-0/+1
2022-02-18drm/i915: Drop pointless i830 PIPECONF readVille Syrjälä1-4/+2
2022-02-18drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical sectionVille Syrjälä1-3/+5
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza1-0/+1
2022-02-18drm/i915: Introduce intel_crtc_planes_update_arm()Ville Syrjälä1-6/+2
2022-02-16drm/i915: Move intel_plane_atomic_calc_changes() & co. outVille Syrjälä1-188/+0
2022-02-15drm/i915: Change bigjoiner state tracking to use the pipe bitmaskVille Syrjälä1-86/+203
2022-02-15drm/i915: Return both master and slave pipes from enabled_bigjoiner_pipes()Ville Syrjälä1-11/+14
2022-02-15drm/i915: Use for_each_intel_crtc_in_pipe_mask() moreVille Syrjälä1-8/+4
2022-02-15drm/i915: Introduce intel_crtc_is_bigjoiner_{slave,master}()Ville Syrjälä1-20/+31
2022-02-11drm/i915: Nuke some dead codeVille Syrjälä1-17/+1
2022-02-11drm/i915: Clean up the bigjoiner state copy logicVille Syrjälä1-62/+108
2022-02-11drm/i915: Remove weird code from intel_atomic_check_bigjoiner()Ville Syrjälä1-22/+11
2022-02-11drm/i915: Fix bigjoiner state copy failsVille Syrjälä1-1/+13
2022-02-11drm/i915: Flag crtc scaling_filter changes as modesetVille Syrjälä1-0/+4
2022-02-09drm/i915: Fix IPS disable in intel_plane_disable_noatomic()Ville Syrjälä1-2/+4
2022-02-09drm/i915: Extract hsw_ips_get_config()Ville Syrjälä1-13/+1
2022-02-09drm/i915: Move the IPS code to its own fileVille Syrjälä1-238/+1
2022-02-09drm/i915: Hoover the IPS enable/disable calls into the pre/post update hooksVille Syrjälä1-12/+34
2022-02-09drm/i915: Change IPS calling conventionVille Syrjälä1-16/+22
2022-02-09drm/i915: Move vblank waits out from IPS codeVille Syrjälä1-7/+12
2022-02-09drm/i915/dpll: add intel_dpll_crtc_compute_clock()Jani Nikula1-1/+1
2022-02-07drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKLVille Syrjälä1-0/+1
2022-02-03drm/i915: Disable unused power wells left enabled by BIOSImre Deak1-0/+2
2022-02-01drm/i915: Document BDW+ DRRS M/N programming requirementsVille Syrjälä1-0/+4
2022-02-01drm/i915: Always check dp_m2_n2 on pre-bdwVille Syrjälä1-6/+5
2022-02-01drm/i915: Dump dp_m2_n2 alwaysVille Syrjälä1-5/+5
2022-02-01drm/i915: Clear DP M2/N2 when not doing DRRSVille Syrjälä1-4/+11
2022-02-01drm/i915: Fix transcoder_has_m2_n2()Ville Syrjälä1-5/+1
2022-02-01drm/i915: Extract {i9xx,ilk}_configure_cpu_transcoder()Ville Syrjälä1-33/+40
2022-02-01drm/i915: Move M/N setup to a more logical place on ddi platformsVille Syrjälä1-4/+10
2022-02-01drm/i915: Move PCH transcoder M/N setup into the PCH codeVille Syrjälä1-46/+16
2022-02-01drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä1-19/+18
2022-02-01drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä1-13/+19
2022-02-01drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä1-33/+42
2022-02-01drm/i915: Nuke ilk_get_fdi_m_n_config()Ville Syrjälä1-7/+0
2022-02-01drm/i915: Nuke intel_dp_get_m_n()Ville Syrjälä1-17/+6
2022-02-01drm/i915: Nuke intel_dp_set_m_n()Ville Syrjälä1-36/+20
2022-02-01Merge tag 'drm-misc-next-2022-01-27' of git://anongit.freedesktop.org/drm/drm...Dave Airlie1-1/+1
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-11/+11
2022-01-28drm/i915: s/gmch_{m,n}/data_{m,n}/Ville Syrjälä1-24/+24
2022-01-28drm/i915: Clean up M/N register definesVille Syrjälä1-5/+5
2022-01-28drm/i915: Extract intel_{get,set}_m_n()Ville Syrjälä1-62/+47
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