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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare1-0/+19
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare1-0/+2
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare1-0/+3
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä1-13/+10
2021-01-21drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä1-4/+3
2021-01-19drm/i915: Fix the PHY compliance test vs. hotplug mishapVille Syrjälä1-0/+8
2021-01-14drm/i915/pps: rename intel_edp_panel_* to intel_pps_*Jani Nikula1-4/+4
2021-01-14drm/i915/pps: abstract panel power sequencer from intel_dp.cJani Nikula1-0/+1
2021-01-13drm/i915/hdcp: Encapsulate hdcp_port_data to dig_portAnshuman Gupta1-0/+2
2021-01-13drm/i915/hdcp: HDCP stream encryption supportAnshuman Gupta1-5/+5
2021-01-13drm/i915/hdcp: DP MST transcoder for link and streamAnshuman Gupta1-1/+1
2021-01-11drm/i915/dg1: Update voltage swing tables for DPMatt Roper1-0/+34
2021-01-11drm/i915: Fix HTI port checkingJosé Roberto de Souza1-2/+1
2021-01-08Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-1/+5
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter1-32/+51
2021-01-06drm/i915/rkl: Add DP vswing programming tablesMatt Roper1-3/+39
2020-12-22drm/i915/display: Let PCON convert from RGB to YCbCr if it canAnkit Nautiyal1-1/+2
2020-12-22drm/i915/display: Configure PCON for DSC1.1 to DSC1.2 encodingAnkit Nautiyal1-0/+1
2020-12-22drm/i915: Check for FRL training before DP Link trainingAnkit Nautiyal1-0/+2
2020-12-07drm/i915/dp: No need to poll FEC Enable Live bitManasi Navare1-6/+0
2020-12-03drm/i915/ddi: Track power reference taken for encoder main lane AUX useImre Deak1-8/+15
2020-12-03drm/i915/ddi: Track power reference taken for encoder DDI IO useImre Deak1-14/+24
2020-12-02drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinksUma Shankar1-1/+5
2020-12-02drm/i915/lspcon: Create separate infoframe_enabled helperUma Shankar1-3/+7
2020-11-18drm/i915: HW state readout for Bigjoiner caseManasi Navare1-9/+28
2020-11-18drm/i915/dp: Master/Slave enable/disable sequence for bigjoinerManasi Navare1-3/+22
2020-11-18drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slaveManasi Navare1-8/+1
2020-11-18drm/i915: Fix the DDI encoder namesVille Syrjälä1-3/+6
2020-11-16drm/i915: Use actual readout results for .get_freq()Ville Syrjälä1-1/+2
2020-11-09drm/i915/edp/jsl: Update vswing table for HBR and HBR2Tejas Upadhyay1-2/+85
2020-11-09drm/i915/dg1: map/unmap pll clocksLucas De Marchi1-3/+88
2020-10-30drm/i915: Give DDI encoders even better namesVille Syrjälä1-2/+25
2020-10-30drm/i915: Add PORT_TCn aliases to enum portVille Syrjälä1-6/+6
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi1-1/+12
2020-10-20drm/i915: s/intel_dp_sink_dpms/intel_dp_set_power/Ville Syrjälä1-3/+3
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-6/+6
2020-10-12drm/i915: Fix DP link training pattern maskImre Deak1-2/+1
2020-10-09drm/i915: Wait for eDP panel power cycle delay on reboot on all platformsVille Syrjälä1-0/+1
2020-10-07drm/i915/display/ehl: Limit eDP to HBR2José Roberto de Souza1-7/+2
2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak1-0/+8
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak1-0/+10
2020-10-01drm/i915: Init lspcon after HPD in intel_dp_detect()Kai-Heng Feng1-18/+1
2020-10-01drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä1-50/+57
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä1-213/+200
2020-10-01drm/i915: Split TGL DKL PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split TGL combo PHY buf trans per output typeVille Syrjälä1-34/+49
2020-10-01drm/i915: Split EHL combo PHY buf trans per output typeVille Syrjälä1-20/+39
2020-10-01drm/i915: Split ICL MG PHY buf trans per output typeVille Syrjälä1-8/+23
2020-10-01drm/i915: Split ICL combo PHY buf trans per output typeVille Syrjälä1-9/+33
2020-10-01drm/i915: Fix TGL DKL PHY DP vswing handlingVille Syrjälä1-1/+1
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