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path: root/drivers/gpu/drm/amd/display/include
AgeCommit message (Expand)AuthorFilesLines
2022-08-16drm/amd/display: add chip revision to DCN32Samson Tam1-1/+3
2022-08-16drm/amd/display: Add reserved dc_log_type.Ian Chen1-1/+3
2022-08-10drm/amd/display: change family id name for DCN314Yifan Zhang1-1/+1
2022-07-13drm/amd/display: Add DCN314 version identifiersRoman Li2-0/+2
2022-07-05drm/amd/display: OVT Update on InfoFrame and Mode ManagementChris Park1-2/+6
2022-06-21drm/amd/display: rename lane_settings to hw_lane_settingsWenjing Liu1-1/+0
2022-06-21drm/amd/display: Remove compiler warningCruise Hung1-1/+1
2022-06-14drm/amd/display: lower lane count first when CR done partially fails in EQWenjing Liu1-0/+2
2022-06-08drm/amd/display: Remove duplicated macroRodrigo Siqueira1-6/+0
2022-06-07drm/amd/display: expose AMD specific DPCD for PSR-SU-RC supportDavid Zhang1-0/+4
2022-06-03drm/amd/display: Fix USBC link creationDillon Varone1-1/+2
2022-06-03drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai1-0/+10
2022-06-03drm/amd/display: Add DCN32/321 version identifiersAurabindo Pillai2-0/+10
2022-06-01drm/amd/display: Don't clear ref_dtbclk valueAlvin1-0/+2
2022-05-26Revert "drm/amd/display: Refactor LTTPR cap retrieval"Michael Strauss1-6/+0
2022-05-19Merge tag 'amd-drm-next-5.19-2022-05-18' of https://gitlab.freedesktop.org/ag...Dave Airlie1-0/+6
2022-05-10drm/amd/display: Refactor LTTPR cap retrievalMichael Strauss1-0/+6
2022-05-06Merge tag 'amd-drm-next-5.19-2022-04-29' of https://gitlab.freedesktop.org/ag...Dave Airlie1-0/+2
2022-04-29Merge tag 'drm-misc-next-2022-04-28' of git://anongit.freedesktop.org/drm/drm...Dave Airlie1-1/+1
2022-04-25drm/amd/display: read PSR-SU cap DPCD for specific panelDavid Zhang1-0/+2
2022-04-25drm: Rename dp/ to display/Thomas Zimmermann1-1/+1
2022-03-31drm/amd/display: Add support for USBC connectorSamson Tam1-0/+1
2022-03-15drm/amd/display: disable HPD SW timer for passive dongle type 1 onlySung Joon Kim1-0/+1
2022-03-15drm/amd/display: cleaning up smu_if to add future flexibilityLeung, Martin1-22/+0
2022-02-23drm/amd/display: Refactor PSR DPCD caps detectionPo Ting Chen1-0/+1
2022-02-18drm/amd/display: Add DCN315 family informationQingqing Zhuo2-0/+7
2022-02-17drm/amd/display: configure dc hw resource for DCN 3.1.6Prike Liang2-1/+6
2022-02-14Merge tag 'amd-drm-next-5.18-2022-02-11-1' of https://gitlab.freedesktop.org/...Dave Airlie7-22/+6
2022-02-11drm/amd/display: extend dcn201 supportOliver Logush1-0/+1
2022-01-25drm/amd/display: Add DSC Enable for Synaptics HubFangzhi Zuo1-0/+3
2022-01-25drm/amd/display: Drop DCN for DP2.x logicWenjing Liu5-22/+0
2022-01-25drm/amd/display: Add work around to enforce TBT3 compatibility.Jimmy Kizito1-0/+2
2022-01-17drm/dp: Move public DisplayPort headers into dp/Thomas Zimmermann1-1/+1
2021-11-22drm/amd/display: Enable DSC over eDPMikita Lipski1-0/+1
2021-11-22drm/amd/display: Drop config guard for DC_LOG_DP2Leo (Hanghong) Ma1-4/+0
2021-11-17drm/amd/display: To support sending TPS3 pattern when restoring linkRobin Chen1-0/+3
2021-11-02Merge tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drmLinus Torvalds10-3/+140
2021-10-28drm/amd/display: add two lane settings training optionsWenjing Liu1-1/+0
2021-10-28drm/amd/display: decouple hw_lane_settings from dpcd_lane_settingsWenjing Liu1-1/+4
2021-10-28drm/amd/display: implement decide lane settingsWenjing Liu1-0/+17
2021-10-28drm/amd/display: Handle I2C-over-AUX write channel status updateAric Cyr1-0/+3
2021-10-28drm/amd/display: Implement fixed DP drive settingsGeorge Shen2-0/+7
2021-10-28BackMerge tag 'v5.15-rc7' into drm-nextDave Airlie1-1/+1
2021-10-20drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu1-1/+1
2021-10-20drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu1-1/+1
2021-10-06drm/amd/display: USB4 bring up set correct addressJude Shih1-1/+1
2021-10-05drm/amd/display: USB4 bring up set correct addressJude Shih1-1/+1
2021-10-04drm/amd/display: add cyan_skillfish display supportZhan Liu2-0/+2
2021-09-14drm/amd/display: Fix for null pointer access for ddc pin and aux engine.Meenakshikumar Somasundaram1-1/+1
2021-09-14drm/amd/display: Add DPCD writes at key pointsLeo (Hanghong) Ma2-0/+17
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