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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
AgeCommit message (Expand)AuthorFilesLines
2017-12-20drm/amd/display: Only blank DCN when we have set_blank implementationYue Hin Lau1-490/+0
2017-12-20drm/amd/display: integrating optc pseudocodeYue Hin Lau1-1/+18
2017-12-14drm/amd/display: OPTC cleanup/implementationYue Hin Lau1-10/+80
2017-12-06drm/amd/display: Add tg_init interface.Yongqiang Sun1-0/+2
2017-12-04drm/amd/display: Adding DCN1 registersMikita Lipski1-3/+30
2017-10-21drm/amd/display: Enable double buffer as per vertical interrupt enabled.Yongqiang Sun1-0/+4
2017-10-21drm/amd/display: removing remaining register definitions work aroundYue Hin Lau1-10/+1
2017-09-26drm/amd/display: Get OTG info if OTG master enabledLogatharshan Thothiralingam1-0/+1
2017-09-26drm/amd/display: Program reg for vertical interrupt.Yongqiang Sun1-0/+4
2017-09-26drm/amd/display: Log OTG registers with dcn10 hw stateCorbin McElhanney1-0/+25
2017-09-26drm/amd/display: ensure OTG is locked before proceedingTony Cheng1-0/+2
2017-09-26drm/amd/display: Rename DCN TG specific function prefixes to tgDmytro Laktyushkin1-25/+28
2017-09-26drm/amd/display: fix dcn pipe reset sequenceDmytro Laktyushkin1-0/+4
2017-09-26drm/amd/display: RV stereo supportVitaly Prosyak1-0/+5
2017-09-26drm/amdgpu/display: Add core dc support for DCNHarry Wentland1-0/+335