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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr
AgeCommit message (Expand)AuthorFilesLines
2022-12-06drm/amd/display: Remove DTB DTO on CLK updateChris Park1-37/+0
2022-11-29drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programmingAlvin Lee1-1/+1
2022-11-23drm/amdgpu: add missing license to some filesAlex Deucher2-0/+2
2022-11-23drm/amd/display: Add Z8 allow states to z-state support listNicholas Kazlauskas2-4/+12
2022-11-17drm/amd/display: Align dcn314_smu logging with other DCNsRoman Li1-2/+9
2022-11-15drm/amd/display: fix dcn3.1x mode validation on high bandwidth configCharlene Liu2-1/+4
2022-11-09drm/amd/display: Update SR watermarks for DCN314Nicholas Kazlauskas1-16/+16
2022-11-01drm/amd/display (gcc13): fix enum mismatchJiri Slaby (SUSE)1-1/+3
2022-10-27drm/amd/display: Set memclk levels to be at least 1 for dcn32Dillon Varone1-0/+3
2022-10-27drm/amd/display: Limit dcn32 to 1950Mhz display clockJun Lei1-4/+4
2022-10-24drm/amd/display: correctly populate dcn315 clock tableDmytro Laktyushkin1-48/+23
2022-10-10drm/amd/display: Fix bug preventing FCLK Pstate allow message being sentDillon Varone1-2/+2
2022-10-10drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone1-14/+27
2022-10-10drm/amd/display: increase hardware status wait timeVladimir Stempen1-2/+2
2022-10-10drm/amd/display: Update PMFW z-state interface for DCN314Nicholas Kazlauskas1-8/+3
2022-10-06drm/amd/display: Reorder FCLK P-state switch sequence for DCN32Dillon Varone1-21/+23
2022-09-29drm/amd/display: fill in clock values when DPM is not enabledSamson Tam1-0/+14
2022-09-29drm/amd/display: Wrap OTG disable workaround with FIFO controlNicholas Kazlauskas1-1/+10
2022-09-19drm/amd/display: Disable OTG WA for the plane_state NULL case on DCN314Nicholas Kazlauskas1-2/+1
2022-09-19drm/amd/display: increase dcn315 pstate change latencyDmytro Laktyushkin1-8/+14
2022-09-19drm/amd/display: Display distortion after hotplug 5K tiled displayMeenakshikumar Somasundaram4-20/+24
2022-09-19drm/amd/display: fix dcn315 memory channel count and width readDmytro Laktyushkin1-2/+1
2022-09-13drm/amd/display: Correct dram channel width for dcn314Duncan Ma1-0/+2
2022-08-25drm/amd/display: Adding log clock table from SMULeo Chen3-0/+140
2022-08-22drm/amd/display: remove unneeded semicolonYang Li1-1/+1
2022-08-16drm/amd/display: Unneeded semicolonmin tang1-1/+1
2022-08-16drm/amd/display: Update clock table policy for DCN314Nicholas Kazlauskas2-65/+154
2022-08-16drm/amd/display: Add debug parameter to retain default clock tableDaniel Miess1-1/+1
2022-08-10drm/amd/display: Correct DTBCLK for dcn314Duncan Ma2-12/+2
2022-08-10drm/amd/display: change family id name for DCN314Yifan Zhang1-2/+2
2022-08-10drm/amd/display: remove header from source fileMagali Lemes2-2/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-2/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-25drm/amd/display: move FPU code from dcn301 clk mgr to DML folderMelissa Wen3-85/+9
2022-07-25drm/amd/display: move FPU code from dcn30 clk mgr to DML folderMelissa Wen2-64/+5
2022-07-25drm/amd/display: move FPU code on dcn21 clk_mgrMelissa Wen3-236/+11
2022-07-25drm/amd/display: Drop FPU flags from dcn32_clk_mgrRodrigo Siqueira2-102/+4
2022-07-13drm/amd/display: Enable DCN314 in DCRoman Li2-1/+30
2022-07-13drm/amd/display: Add DCN314 clock managerRoman Li4-0/+1278
2022-07-12drm/amd/display: Removing assert statements for LinuxSaaem Rizvi5-9/+30
2022-07-05drm/amd/display: disable otg toggle w/a on bootDmytro Laktyushkin1-2/+5
2022-07-05drm/amd/display: Switch to correct DTO on HDMIChris Park1-0/+2
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee2-2/+9
2022-06-30drm/amdgpu/display: add missing FP_START/END checks dcn32_clk_mgr.cAlex Deucher1-0/+4
2022-06-30drm/amd/display: Fix __nedf2 undefined for 32 bit compilationRodrigo Siqueira1-4/+7
2022-06-30drm/amd/display: Fix __muldf3 undefined for 32 bit compilationRodrigo Siqueira1-2/+2
2022-06-23drm/amd/display: Fix indentation in dcn32_get_vco_frequency_from_reg()Nathan Chancellor1-1/+1
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