summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu
AgeCommit message (Expand)AuthorFilesLines
2020-07-01drm/amdgpu: support reserve bad page for virt (v3)Stanley.Yang3-4/+202
2020-07-01drm/amdgpu/fence: use the no_scheduler flagAlex Deucher1-4/+4
2020-07-01Revert "drm/[radeon|amdgpu]: Replace one-element array and use struct_size() ...Alex Deucher2-3/+4
2020-07-01drm/amdgpu: temporarily read bounding box from gpu_info fw for navi12Tianci.Yin1-1/+15
2020-07-01drm/amdgpu: Enable DM block for DCN3Bhawanpreet Lakha1-0/+4
2020-07-01drm/amdgpu: bypass tmr when reserve c2p memoryLikun Gao1-29/+19
2020-07-01drm/amdgpu: remove unnecessary check for mem trainLikun Gao5-58/+7
2020-07-01drm/amdgpu: support memory training for sienna_cichlidLikun Gao1-1/+3
2020-07-01drm/amdgpu: reserve fb according to return value from vbiosLikun Gao1-56/+71
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-0/+2
2020-07-01drm/amdgpu/psp: support for loading PSP SPL fwLikun Gao3-0/+46
2020-07-01drm/amdgpu/psp: initialization PSP SPL fwLikun Gao2-0/+37
2020-07-01drm/amdgpu/psp: add structure to support PSP SPLLikun Gao2-0/+11
2020-07-01drm/amdgpu: enable gfxoff for sienna_cichlidLikun Gao1-3/+1
2020-07-01drm/amdgpu/sriov : Add sriov detection for sienna_cichlidshaoyunl1-0/+1
2020-07-01drm/amdgpu: only use one gfx pipe for Sienna_CichlidLikun Gao1-2/+2
2020-07-01drm/amdgpu: disable runtime pm for sienna_cichlid temporarilyLikun Gao1-0/+1
2020-07-01drm/amdgpu: skip GPU scheduler setup for KIQ and MES ringLikun Gao1-1/+1
2020-07-01drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriovshaoyunl2-0/+21
2020-07-01drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encodeAlex Deucher1-0/+4
2020-07-01drm/amdgpu/mes10.1: add no scheduler flag for mesAlex Deucher1-0/+1
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang2-2/+6
2020-07-01drm/amdgpu: add workaround for issue in DPG for VCN3.0Boyuan Zhang1-0/+4
2020-07-01drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0Boyuan Zhang4-137/+137
2020-07-01drm/amdgpu: rename macro for VCN1.0Boyuan Zhang2-50/+50
2020-07-01drm/amdgpu: add internal reg offset translation for VCN inst 1Boyuan Zhang1-1/+13
2020-07-01drm/amdgpu: set indirect sram mode for VCN3.0Boyuan Zhang1-0/+3
2020-07-01drm/amdgpu: add pause DPG mode for VCN3.0Boyuan Zhang1-0/+66
2020-07-01drm/amdgpu: add stop DPG mode for VCN3.0Boyuan Zhang1-0/+34
2020-07-01drm/amdgpu: add start DPG mode for VCN3.0Boyuan Zhang1-0/+141
2020-07-01drm/amdgpu: add mc resume DPG mode for VCN3.0Boyuan Zhang1-0/+89
2020-07-01drm/amdgpu: add clock gating DPG mode for VCN3.0Boyuan Zhang1-0/+48
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-1/+1
2020-07-01drm/amd/powerplay: enable mmhub pgKenneth Feng1-1/+2
2020-07-01drm/amd/powerplay: enable athub pgKenneth Feng1-1/+2
2020-07-01drm/amdgpu: skip VM inv eng assignment for mes ringLe Ma1-0/+3
2020-07-01drm/amdgpu/mes: allocate memory slots for hw resource settingLe Ma1-0/+36
2020-07-01drm/amdgpu/mes: add status fence memory definitionsLe Ma2-0/+5
2020-07-01drm/amdgpu/mes: update mes fw apiLe Ma1-303/+341
2020-07-01drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOVshaoyunl1-1/+1
2020-07-01drm/amdgpu: fix typo for vcn3/jpeg3 idle checkJames Zhu2-2/+2
2020-07-01drm/amdkfd: Support Sienna_Cichlid KFD v4Yong Zhao2-6/+841
2020-07-01drm/amdgpu/dc: Add missing Sienna_Cichlid chip idJerry (Fangzhi) Zuo1-0/+3
2020-07-01drm/amdgpu: enable 3D pipe 1 on Sienna_CichlidLikun Gao1-1/+13
2020-07-01drm/amdgpu: fix SDMA hdp flush engine conflictLikun Gao1-4/+2
2020-07-01drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.Likun Gao1-0/+1
2020-07-01drm/amd/amdgpu: add athub ls supportKenneth Feng1-1/+2
2020-07-01drm/amd/amdgpu: add IH cg supportKenneth Feng1-1/+2
2020-07-01drm/amd/amdgpu: add HDP mgcg and ls supportKenneth Feng1-1/+3
2020-07-01drm/amd/amdgpu: fix the HDP LS/DS/SD programmingKenneth Feng1-0/+10