summaryrefslogtreecommitdiffstats
path: root/drivers/fpga/zynq-fpga.c
AgeCommit message (Expand)AuthorFilesLines
2020-03-30fpga: zynq: Remove clk_get error message for probe deferShubhrajyoti Datta1-1/+2
2019-10-04fpga: Remove dev_err() usage after platform_get_irq()Stephen Boyd1-3/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285Thomas Gleixner1-9/+1
2018-11-11zynq-fpga: Only route PR via PCAP when requiredMike Looijmans1-0/+4
2018-10-16fpga: mgr: add devm_fpga_mgr_createAlan Tull1-3/+2
2018-05-25fpga: manager: change api, don't use drvdataAlan Tull1-3/+11
2017-03-17fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer1-3/+25
2017-02-10fpga zynq: Use the scatterlist interfaceJason Gunthorpe1-39/+135
2017-02-10fpga zynq: Check the bitstream for validityJason Gunthorpe1-0/+21
2017-02-10fpga zynq: Check for errors after completing DMAJason Gunthorpe1-22/+32
2016-11-29fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe1-7/+10
2016-11-29fpga zynq: Remove priv->devJason Gunthorpe1-11/+8
2016-11-29fpga zynq: Add missing \n to messagesJason Gunthorpe1-11/+11
2016-11-10fpga-mgr: add fpga image information structAlan Tull1-4/+6
2015-10-23fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer1-3/+4
2015-10-23fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer1-22/+2
2015-10-23fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer1-2/+2
2015-10-17fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer1-0/+533