summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/pci.c
AgeCommit message (Expand)AuthorFilesLines
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)1-2/+2
2021-09-07cxl/pci: Fix lockdown levelDan Williams1-1/+1
2021-08-10cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny1-8/+6
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny1-5/+91
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny1-3/+33
2021-08-06cxl/pci: Simplify register setupBen Widawsky1-26/+12
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky1-8/+12
2021-08-06cxl/core: Move memdev management to coreBen Widawsky1-227/+1
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams1-27/+38
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky1-1/+1
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky1-1/+1
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-6/+17
2021-06-14cxl/pci: Add media provisioning required commandsBen Widawsky1-0/+19
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-0/+15
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny1-0/+2
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny1-21/+90
2021-06-05cxl/pci: Reserve all device regions at onceIra Weiny1-7/+11
2021-06-05cxl/pci: Introduce cxl_decode_register_block()Ira Weiny1-8/+18
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky1-13/+11
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky1-67/+68
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky1-24/+40
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky1-1/+1
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma1-0/+12
2021-05-26cxl: Rename mem to pciBen Widawsky1-0/+1524