linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2022-02-08	cxl/core/port: Add endpoint decoders	Ben Widawsky	1	-0/+1
2022-02-08	cxl/mem: Add the cxl_mem driver	Ben Widawsky	1	-0/+6
2022-02-08	cxl/core/port: Add switch port enumeration	Dan Williams	1	-0/+19
2022-02-08	cxl/core/port: Remove @host argument for dport + decoder enumeration	Dan Williams	1	-4/+4
2022-02-08	cxl/port: Add a driver for 'struct cxl_port' objects	Ben Widawsky	1	-0/+4
2022-02-08	cxl/core/hdm: Add CXL standard decoder enumeration to the core	Dan Williams	1	-6/+27
2022-02-08	cxl/core: Generalize dport enumeration in the core	Dan Williams	1	-12/+4
2022-02-08	cxl/pmem: Introduce a find_cxl_root() helper	Dan Williams	1	-0/+1
2022-02-08	cxl/port: Introduce cxl_port_to_pci_bus()	Dan Williams	1	-0/+3
2022-02-08	cxl/core/port: Use dedicated lock for decoder target list	Dan Williams	1	-0/+2
2022-02-08	cxl: Prove CXL locking	Dan Williams	1	-0/+81
2022-02-08	cxl/core: Track port depth	Ben Widawsky	1	-0/+2
2022-02-08	cxl/core/port: Clarify decoder creation	Ben Widawsky	1	-1/+15
2022-02-08	cxl/core: Convert decoder range to resource	Ben Widawsky	1	-2/+6
2022-02-08	cxl: Introduce module_cxl_driver	Ben Widawsky	1	-0/+3
2022-02-08	cxl/acpi: Map component registers for Root Ports	Ben Widawsky	1	-0/+4
2022-01-04	cxl/core: Remove cxld_const_init in cxl_decoder_alloc()	Nathan Chancellor	1	-1/+1
2021-11-15	cxl/pmem: Fix module reload vs workqueue state	Dan Williams	1	-0/+8
2021-11-08	Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...	Linus Torvalds	1	-19/+39
2021-10-29	cxl/pci: Add @base to cxl_register_map	Dan Williams	1	-0/+10
2021-09-25	cxl/core: Replace unions with struct_group()	Kees Cook	1	-43/+18
2021-09-21	cxl/core: Split decoder setup into alloc + add	Dan Williams	1	-9/+6
2021-09-21	tools/testing/cxl: Introduce a mock memory device + driver	Dan Williams	1	-1/+1
2021-09-21	cxl/bus: Populate the target list at decoder create	Dan Williams	1	-15/+10
2021-09-21	tools/testing/cxl: Introduce a mocked-up CXL port hierarchy	Dan Williams	1	-0/+16
2021-09-21	cxl/pmem: Add support for multiple nvdimm-bridge objects	Dan Williams	1	-0/+2
2021-08-06	cxl/pci: Simplify register setup	Ben Widawsky	1	-1/+0
2021-06-15	cxl/pmem: Register 'pmem' / cxl_nvdimm devices	Dan Williams	1	-1/+11
2021-06-15	cxl/pmem: Add initial infrastructure for pmem support	Dan Williams	1	-0/+24
2021-06-15	cxl/core: Add cxl-bus driver infrastructure	Dan Williams	1	-0/+22
2021-06-12	cxl/hdm: Fix decoder count calculation	Ben Widawsky	1	-0/+7
2021-06-09	cxl/acpi: Introduce cxl_decoder objects	Dan Williams	1	-0/+63
2021-06-09	cxl/acpi: Add downstream port data to cxl_port instances	Dan Williams	1	-0/+21
2021-06-09	cxl/acpi: Introduce the root of a cxl_port topology	Dan Williams	1	-0/+31
2021-06-05	cxl/pci: Add HDM decoder capabilities	Ben Widawsky	1	-6/+59
2021-06-05	cxl/pci: Map registers based on capabilities	Ira Weiny	1	-5/+28
2021-05-14	cxl/core: Refactor CXL register lookup for bridge reuse	Dan Williams	1	-0/+3
2021-05-14	cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices	Dan Williams	1	-0/+32
2021-05-14	cxl/mem: Move some definitions to mem.h	Dan Williams	1	-57/+0
2021-02-16	cxl/mem: Enable commands via CEL	Ben Widawsky	1	-0/+2
2021-02-16	cxl/mem: Register CXL memX devices	Dan Williams	1	-0/+3
2021-02-16	cxl/mem: Find device capabilities	Ben Widawsky	1	-0/+90