index
:
linux
WIP-syscall
master
mmu_gather-race-fix
n900-dt
n900-dt-with-ssi
n900-dts-twl5030
n900-modem-rework
n900-omapdrm
next
proc-cmdline
sc18is600
ssi
ssi-cleaned
ssi-cleaned-dt
ssi-cleaned-dt2
ssi-cleaned-dt3
tty-splice
twl4030-madc-cleanup
Linux Kernel (branches are rebased on master from time to time)
Linus Torvalds
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
acpi.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-10-08
cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBS
Alison Schofield
1
-4
/
+6
2021-09-21
cxl/core: Split decoder setup into alloc + add
Dan Williams
1
-24
/
+60
2021-09-21
cxl/bus: Populate the target list at decoder create
Dan Williams
1
-1
/
+12
2021-09-21
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams
1
-15
/
+21
2021-09-07
cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports
Alison Schofield
1
-4
/
+8
2021-06-17
cxl/acpi: Use the ACPI CFMWS to create static decoder objects
Alison Schofield
1
-0
/
+122
2021-06-17
cxl/acpi: Add the Host Bridge base address to CXL port objects
Alison Schofield
1
-5
/
+95
2021-06-15
cxl/pmem: Add initial infrastructure for pmem support
Dan Williams
1
-2
/
+35
2021-06-09
cxl/acpi: Introduce cxl_decoder objects
Dan Williams
1
-1
/
+19
2021-06-09
cxl/acpi: Enumerate host bridge root ports
Dan Williams
1
-1
/
+92
2021-06-09
cxl/acpi: Add downstream port data to cxl_port instances
Dan Williams
1
-1
/
+42
2021-06-09
cxl/acpi: Introduce the root of a cxl_port topology
Dan Williams
1
-0
/
+39