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path: root/drivers/clk
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2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das3-64/+93
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das2-0/+5
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das1-3/+3
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das1-3/+4
2021-07-12clk: renesas: rzg2l: Add multi clock PM supportBiju Das1-22/+29
2021-07-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds6-54/+101
2021-07-02Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-0/+4
2021-07-01Revert "clk: divider: Switch from .round_rate to .determine_rate by default"Stephen Boyd1-9/+9
2021-07-01Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds95-1191/+16314
2021-07-01kernel.h: split out panic and oops helpersAndy Shevchenko1-0/+4
2021-06-30clk: hisilicon: hi3559a: Drop __init markings everywhereStephen Boyd1-20/+19
2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl1-10/+9
2021-06-30clk: divider: Switch from .round_rate to .determine_rate by defaultMartin Blumenstingl1-9/+9
2021-06-30clk: divider: Add re-usable determine_rate implementationsMartin Blumenstingl1-14/+61
2021-06-30clk: k210: Fix k210_clk_set_parent()Damien Le Moal1-0/+1
2021-06-30clk: lmk04832: Fix spelling mistakes in dev_err messages and commentsColin Ian King1-4/+4
2021-06-30clk: lmk04832: fix return value check in lmk04832_probe()Wang Hai1-6/+6
2021-06-30clk: stm32mp1: fix missing spin_lock_init()Wang Hai1-0/+1
2021-06-29Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-nextStephen Boyd9-73/+1710
2021-06-29Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-...Stephen Boyd15-186/+2625
2021-06-29Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk...Stephen Boyd18-113/+449
2021-06-29Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl...Stephen Boyd23-296/+931
2021-06-29Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and '...Stephen Boyd19-92/+1414
2021-06-28clk: zynqmp: Handle divider specific read only flagRajan Vaja1-1/+9
2021-06-28clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja2-1/+30
2021-06-28clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja2-1/+33
2021-06-28clk: zynqmp: Use firmware specific common clock flagsRajan Vaja6-6/+52
2021-06-28clk: lmk04832: Use of match tableStephen Boyd1-2/+4
2021-06-28clk: lmk04832: Depend on SPIStephen Boyd1-0/+1
2021-06-28clk: stm32mp1: new compatible for secure RCC supportGabriel Fernandez2-1/+110
2021-06-27clk: hisilicon: Add clock driver for hi3559A SoCDongjiu Geng5-2/+856
2021-06-27clk: si5341: Add sysfs properties to allow checking/resetting device faultsRobert Hancock1-0/+96
2021-06-27clk: si5341: Add silabs,iovdd-33 propertyRobert Hancock1-1/+9
2021-06-27clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock1-2/+7
2021-06-27clk: si5341: Allow different output VDD_SEL valuesRobert Hancock1-26/+110
2021-06-27clk: si5341: Update initialization magicRobert Hancock1-1/+3
2021-06-27clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock1-0/+26
2021-06-27clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock1-2/+13
2021-06-27clk: si5341: Wait for DEVICE_READY on startupRobert Hancock1-0/+32
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua1-4/+1
2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat1-12/+101
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat1-14/+106
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat1-14/+353
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat1-1/+0
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil4-0/+441
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2-13/+30
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil3-8/+6
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil1-8/+11
2021-06-27clk: Support bypassing dividersPaul Cercueil5-29/+42
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1