linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2018-12-11	clk: Tag basic clk types with SPDX	Stephen Boyd	9	-46/+9
2018-12-11	clk: Tag clk core files with SPDX	Stephen Boyd	5	-32/+5
2018-12-11	clk: meson: axg-audio: use the clk input helper function	Jerome Brunet	1	-59/+24
2018-12-10	clk: Loongson1: Remove usage of CLK_IS_BASIC	Stephen Boyd	1	-3/+5
2018-12-10	clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC	Stephen Boyd	1	-1/+1
2018-12-10	clk: versatile: sp810: Remove usage of CLK_IS_BASIC	Stephen Boyd	1	-1/+1
2018-12-10	clk: hisilicon: Remove usage of CLK_IS_BASIC	Stephen Boyd	4	-4/+4
2018-12-10	clk: h8300: Remove usage of CLK_IS_BASIC	Stephen Boyd	1	-1/+1
2018-12-10	clk: axm5516: Remove usage of CLK_IS_BASIC	Stephen Boyd	1	-2/+0
2018-12-10	clk: st: Remove usage of CLK_IS_BASIC	Stephen Boyd	3	-4/+4
2018-12-10	clk: renesas: Remove usage of CLK_IS_BASIC	Stephen Boyd	5	-8/+8
2018-12-10	clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock	Matti Vaittinen	3	-0/+131
2018-12-10	clk: qcom: Move to menuconfig and reduce lines	Stephen Boyd	1	-35/+10
2018-12-10	clk: imx6q: handle ENET PLL bypass	Lucas Stach	1	-6/+57
2018-12-10	clk: imx6q: optionally get CCM inputs via standard clock handles	Lucas Stach	1	-5/+17
2018-12-10	clk: imx6q: reset exclusive gates on init	Lucas Stach	1	-1/+5
2018-12-10	clk: imx6q: add DCICx clocks gate	Anson Huang	1	-0/+2
2018-12-10	clk: imx6sl: ensure MMDC CH0 handshake is bypassed	Anson Huang	1	-0/+6
2018-12-10	clk: qcom: qcs404: Fix gpll0_out_main parent	Srinivas Kandagatla	1	-1/+1
2018-12-10	clk: sunxi-ng: a64: Allow parent change for VE clock	Jernej Skrabec	1	-1/+1
2018-12-10	clk: imx: remove redundant initialization of ret to zero	Colin Ian King	1	-1/+1
2018-12-07	Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...	Stephen Boyd	8	-33/+46
2018-12-07	clk: renesas: rcar-gen3: Add HS400 quirk for SD clock	Niklas Söderlund	1	-7/+26
2018-12-07	clk: renesas: rcar-gen3: Add documentation for SD clocks	Niklas Söderlund	1	-5/+5
2018-12-07	clk: renesas: rcar-gen3: Set state when registering SD clocks	Niklas Söderlund	1	-12/+4
2018-12-05	clk: qcom: gcc-msm8998: Add clkref clocks	Bjorn Andersson	1	-0/+75
2018-12-05	clk: qcom: gcc-msm8998: Disable halt check of UFS clocks	Bjorn Andersson	1	-3/+3
2018-12-05	clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at	Bjorn Andersson	1	-28/+0
2018-12-05	clk: qcom: Enumerate remaining msm8998 resets	Jeffrey Hugo	1	-0/+87
2018-12-05	clk: qcom: Add xo dummy clk on msm8998	Stephen Boyd	1	-0/+15
2018-12-05	clk: mediatek: fix the PCIe MAC clock parent	Ryder Lee	1	-2/+2
2018-12-05	clk: apcs-msm8916: simplify probe cleanup by using devm	Matti Vaittinen	1	-4/+2
2018-12-05	clk: clk-twl6040: Free of_provider at remove	Matti Vaittinen	1	-3/+2
2018-12-05	clk: rk808: use managed version of of_provider registration	Matti Vaittinen	1	-13/+2
2018-12-05	clk: clk-hi655x: Free of_provider at remove	Matti Vaittinen	1	-2/+2
2018-12-05	clk: of-provider: look at parent if registered device has no provider info	Matti Vaittinen	1	-4/+27
2018-12-05	clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks	Chen-Yu Tsai	1	-3/+3
2018-12-05	clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-13/+24
2018-12-05	clk: meson: add clk-input helper function	Jerome Brunet	3	-0/+50
2018-12-04	clk: Add kerneldoc to managed of-provider interfaces	Matti Vaittinen	1	-0/+15
2018-12-04	clk: renesas: r8a77995: Simplify PLL3 multiplier/divider	Geert Uytterhoeven	1	-2/+2
2018-12-04	clk: renesas: r8a77995: Add missing CPEX clock	Geert Uytterhoeven	1	-1/+2
2018-12-04	clk: renesas: r8a77995: Remove non-existent SSP clocks	Geert Uytterhoeven	1	-1/+0
2018-12-04	clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks	Geert Uytterhoeven	1	-3/+0
2018-12-04	clk: renesas: r8a77995: Correct parent clock of DU	Geert Uytterhoeven	1	-2/+2
2018-12-04	clk: renesas: r8a77990: Correct parent clock of DU	Takeshi Kihara	1	-2/+2
2018-12-04	clk: renesas: r8a77970: Add CPEX clock	Geert Uytterhoeven	1	-0/+1
2018-12-04	clk: renesas: r8a77965: Add CPEX clock	Geert Uytterhoeven	1	-0/+1
2018-12-04	clk: renesas: r8a7796: Add CPEX clock	Geert Uytterhoeven	1	-0/+1
2018-12-04	clk: renesas: r8a7795: Add CPEX clock	Geert Uytterhoeven	1	-0/+1