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path: root/drivers/clk/tegra
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2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner20-240/+20
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner5-49/+5
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd4-40/+77
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd1-1/+1
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko1-1/+2
2019-04-25clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko1-1/+4
2019-04-25clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko1-7/+10
2019-04-25clk: tegra: emc: Support multiple RAM codesDmitry Osipenko1-14/+23
2019-04-25clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko1-2/+0
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko1-2/+1
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko1-2/+2
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2-5/+5
2019-04-19clk: tegra: Don't enable already enabled PLLsDmitry Osipenko1-13/+37
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing1-1/+1
2019-03-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-9/+9
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd1-9/+9
2019-02-22clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing1-9/+9
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann7-98/+913
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2-0/+427
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo1-8/+13
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo1-67/+377
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo4-14/+59
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver1-11/+34
2019-01-09clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter1-1/+3
2018-12-14Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd10-32/+80
2018-12-14clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang1-3/+4
2018-12-14clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter1-3/+3
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter7-13/+37
2018-12-14clk: tegra: get rid of duplicate definesMarcel Ziswiler1-3/+0
2018-11-28clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li1-11/+1
2018-11-08clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko1-0/+10
2018-11-08clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko1-10/+26
2018-10-16clk: tegra210: Include size.h for compilation easeStephen Boyd1-0/+1
2018-10-16clk: tegra: Fixes for MBIST work aroundJoseph Lo1-3/+3
2018-10-16clk: tegra: probe deferral error reportingMarcel Ziswiler1-2/+6
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd8-40/+343
2018-08-14Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd4-7/+15
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver3-15/+12
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver3-0/+278
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver4-25/+52
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo1-0/+1
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1