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path: root/drivers/clk/tegra
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2020-03-24clk: tegra: Use NULL for pointer initializationStephen Boyd1-1/+1
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni5-15/+10
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni9-201/+19
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni6-45/+0
2020-03-12clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni1-6/+6
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni6-0/+14
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni6-0/+34
2020-01-31Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '...Stephen Boyd5-11/+15
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko2-2/+2
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko2-4/+0
2020-01-10clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko1-2/+7
2020-01-10clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni1-2/+1
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren1-1/+5
2019-12-24clk: tegra: Fix double-free in tegra_clk_init()Dmitry Osipenko1-1/+3
2019-11-13clk: tegra: Use match_string() helper to simplify the codeYueHaibing1-8/+4
2019-11-11clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing1-0/+2
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko2-18/+32
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni3-4/+163
2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2-45/+45
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni1-4/+4
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni3-0/+59
2019-11-11clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni1-0/+27
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni4-1/+39
2019-11-11clk: tegra: periph: Add restore_context supportSowjanya Komatineni2-0/+37
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2-0/+16
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni1-32/+54
2019-11-11clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni1-0/+9
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni1-0/+11
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding1-16/+55
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding1-9/+13
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding3-8/+8
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2-8/+49
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding2-2/+2
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko5-52/+339
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-8/+12
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+2
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding1-1/+0
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding1-1/+5
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding1-2/+3
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo1-4/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter1-0/+2
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner20-240/+20
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner5-49/+5
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd4-40/+77
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd1-1/+1
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko1-1/+2