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path: root/drivers/clk/tegra
AgeCommit message (Expand)AuthorFilesLines
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter1-4/+4
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver3-0/+19
2017-04-04clk: tegra: Propagate clk_out_x rate to parentAlex Frid1-2/+4
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding2-2/+2
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver1-0/+2
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver1-0/+25
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver1-0/+85
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver2-197/+272
2017-03-20clk: tegra: Implement reset control resetMikko Perttunen1-0/+16
2017-03-20clk: tegra: Fix disable unused for clocks sharing enable bitPeter De Schrijver1-0/+3
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver1-0/+26
2017-03-20clk: tegra: Add aclkPeter De Schrijver1-0/+10
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver2-5/+89
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver3-1/+28
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver2-4/+4
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver3-24/+73
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver6-0/+6
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver1-1/+1
2017-03-20clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver1-1/+7
2017-03-20clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver1-6/+12
2017-03-20clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver1-5/+0
2017-03-20clk: tegra: Correct afi clock parentPeter De Schrijver1-1/+1
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver3-2/+11
2017-03-20clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver1-1/+2
2017-02-25Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds3-0/+625
2017-02-03clk: tegra: Add BPMP clock driverThierry Reding3-0/+625
2017-01-30PM / OPP: Update OPP users to put referenceViresh Kumar1-11/+6
2016-11-10clk: tegra: dfll: Use builtin_platform_driver to simplify the codeWei Yongjun1-6/+1
2016-11-04clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modularPaul Gortmaker1-14/+2
2016-11-01clk: tegra: dfll: improve function-level documentationJulia Lawall1-5/+5
2016-08-24clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu1-2/+2
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker6-598/+531
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding1-4/+4
2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding1-2/+2
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding1-1/+1
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding1-0/+2
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2-12/+12
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding1-2/+3
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding1-47/+47
2016-05-27remove lots of IS_ERR_VALUE abusesArnd Bergmann1-1/+1
2016-05-20Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds19-114/+369
2016-05-18Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-0/+58
2016-05-09Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann1-0/+58
2016-05-02Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd19-114/+427
2016-04-28clk: tegra: dfll: Reformat CVB frequency tableThierry Reding1-25/+25
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding4-4/+48
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding3-41/+37
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding3-27/+17
2016-04-28clk: tegra: dfll: Update kerneldocThierry Reding1-5/+5
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6