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path: root/drivers/clk/tegra
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2015-10-20Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette7-113/+163
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein5-11/+56
2015-10-20clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding1-3/+15
2015-10-20clk: tegra: Fix comments for structure definitionsRhyland Klein1-37/+37
2015-10-20clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding1-50/+49
2015-10-12clk: tegra: delete unneeded of_node_putJulia Lawall1-3/+1
2015-09-16clk: tegra: dfll: Properly protect OPP listThierry Reding1-1/+7
2015-09-15clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2-14/+8
2015-08-25clk: tegra: Fix some static checker problemsStephen Boyd2-7/+9
2015-08-25Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd10-9/+2304
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd1-4/+4
2015-08-24clk: tegra: Convert to clk_hw based provider APIsStephen Boyd2-10/+10
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd16-16/+2
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-13/+15
2015-07-20clk: tegra: Properly include clk.hStephen Boyd16-16/+2
2015-07-16clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen1-1/+3
2015-07-16clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen1-0/+14
2015-07-16clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen4-4/+172
2015-07-16clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley1-0/+68
2015-07-16clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2-8/+34
2015-07-16clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen2-0/+207
2015-07-16clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen1-3/+663
2015-07-16clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen3-0/+1150
2015-05-13clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler1-1/+1
2015-05-13clk: tegra: EMC clock driver depends on EMC driverThierry Reding3-1/+14
2015-05-13clk: tegra: Have EMC clock implement determine_rate()Tomeu Vizoso1-12/+23
2015-05-13clk: tegra: Set the EMC clock as the parent of the MC clockTomeu Vizoso1-12/+1
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen4-2/+535
2015-05-13clk: tegra: Remove old Tegra124 EMC clockMikko Perttunen1-1/+0
2015-04-10clk: tegra: Use the proper parent for plld_dsiThierry Reding1-6/+8
2015-04-10clk: tegra: Use generic tegra_osc_clk_init() on Tegra114Thierry Reding1-31/+3
2015-04-10clk: tegra: Model oscillator as clockThierry Reding4-17/+21
2015-04-10clk: tegra: Add peripheral registers for bank YThierry Reding1-0/+14
2015-04-10clk: tegra: Register the proper number of resetsThierry Reding1-1/+1
2015-04-10clk: tegra: Remove needless initializationsThierry Reding1-3/+3
2015-04-10clk: tegra: Use consistent indentationThierry Reding1-10/+10
2015-04-10clk: tegra: Various whitespace cleanupsThierry Reding2-1/+2
2015-04-10clk: tegra: Enable HDA to HDMI clocks on Tegra124Dylan Reid1-0/+5
2015-04-10clk: tegra: Fix a bunch of sparse warningsThierry Reding1-1/+1
2015-04-10clk: tegra: Fix typo tabel -> tableThierry Reding1-1/+1
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas1-7/+7
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang4-26/+24
2015-02-02clk: tegra: Add support for the Tegra132 CAR IP blockPaul Walmsley3-12/+129
2015-02-02clk: tegra: make tegra_clocks_apply_init_table() arch_initcallPeter De Schrijver1-2/+5
2015-02-02clk: tegra: Fix order of arguments in WARNTomeu Vizoso1-4/+4
2015-02-02clk: tegra124: Add init data for dsi lp clocksSean Paul1-0/+2
2015-02-02clk: tegra: SDMMC controllers are on APBAndrew Bresticker1-8/+8
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding6-4/+40
2014-09-18clk: tegra: Make clock initialization more robustTomeu Vizoso1-2/+7
2014-09-18clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen1-0/+8