linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2014-02-17	clk: tegra: PLLD2 fixes for hdmi	David Ung	1	-8/+7
2014-02-17	clk: tegra: Fix PLLD mnp table	Rhyland Klein	1	-1/+10
2014-02-17	clk: tegra: Fix PLLP rate table	Gabe Black	1	-5/+5
2014-02-17	clk: tegra: Correct clock number for UARTE	Thierry Reding	1	-1/+1
2014-02-17	clk: tegra: Add missing Tegra20 fuse clks	Peter De Schrijver	1	-0/+2
2014-01-23	Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turq...	Linus Torvalds	2	-7/+7
2013-12-19	clk: tegra: Staticize tegra_clk_periph_nodiv_ops	Sachin Kamat	1	-1/+1
2013-12-19	clk: tegra: Staticize local variables in clk-pll.c	Sachin Kamat	1	-6/+6
2013-12-11	clk: tegra: remove bogus PCIE_XCLK	Stephen Warren	2	-13/+0
2013-12-11	clk: tegra: remove legacy reset APIs	Stephen Warren	3	-63/+0
2013-12-11	clk: tegra: implement a reset driver	Stephen Warren	6	-6/+57
2013-11-28	clk: tegra: fix __clk_lookup() return value checks	Wei Yongjun	1	-4/+4
2013-11-28	clk: tegra: Do not print errors for clk_round_rate()	Thierry Reding	1	-6/+3
2013-11-26	clk: tegra: Initialize DSI low-power clocks	Thierry Reding	1	-0/+2
2013-11-26	clk: tegra: add FUSE clock device	Alexandre Courbot	4	-1/+4
2013-11-26	clk: tegra: Properly setup PWM clock on Tegra30	Thierry Reding	1	-1/+3
2013-11-26	clk: tegra: Initialize secondary gr3d clock on Tegra30	Thierry Reding	1	-0/+1
2013-11-26	clk: tegra114: Initialize clocks needed for HDMI	Mikko Perttunen	1	-0/+2
2013-11-26	clk: tegra124: add suspend/resume function for tegra_cpu_car_ops	Joseph Lo	1	-0/+27
2013-11-26	clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops	Joseph Lo	1	-0/+26
2013-11-26	clk: tegra124: Add support for Tegra124 clocks	Peter De Schrijver	2	-0/+1371
2013-11-26	clk: tegra124: Add new peripheral clocks	Peter De Schrijver	1	-0/+69
2013-11-26	clk: tegra124: Add common clk IDs to clk-id.h	Peter De Schrijver	1	-0/+22
2013-11-26	clk: tegra: add TEGRA_PERIPH_NO_GATE	Peter De Schrijver	3	-3/+22
2013-11-26	clk: tegra: add locking to periph clks	Peter De Schrijver	2	-19/+24
2013-11-26	clk: tegra: Add periph regs bank X	Peter De Schrijver	1	-0/+10
2013-11-26	clk: tegra: Add support for PLLSS	Peter De Schrijver	2	-2/+126
2013-11-26	clk: tegra: move tegra20 to common infra	Peter De Schrijver	1	-402/+255
2013-11-26	clk: tegra: move tegra30 to common infra	Peter De Schrijver	1	-895/+403
2013-11-26	clk: tegra: introduce common gen4 super clock	Peter De Schrijver	4	-74/+155
2013-11-26	clk: tegra: move PMC, fixed clocks to common files	Peter De Schrijver	5	-74/+253
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	6	-581/+627
2013-11-26	clk: tegra: move audio clk to common file	Peter De Schrijver	4	-208/+402
2013-11-26	clk: tegra: add clkdev registration infra	Peter De Schrijver	3	-159/+179
2013-11-26	clk: tegra: add common infra for DT clocks	Peter De Schrijver	2	-0/+16
2013-11-26	clk: tegra: add header for common tegra clock IDs	Peter De Schrijver	1	-0/+213
2013-11-26	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver	5	-177/+175
2013-11-26	clk: tegra: use pll_ref as the pll_e parent	Peter De Schrijver	2	-4/+7
2013-11-26	clk: tegra: move some PLLC and PLLXC init to clk-pll.c	Peter De Schrijver	2	-93/+111
2013-11-26	clk: tegra: Add TEGRA_PERIPH_NO_DIV flag	Peter De Schrijver	2	-3/+9
2013-11-26	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver	6	-108/+85
2013-11-26	clk: tegra: simplify periph clock data	Peter De Schrijver	7	-584/+464
2013-11-26	clk: tegra: Fix clock rate computation	Thierry Reding	1	-0/+2
2013-11-26	clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d	Thierry Reding	1	-4/+4
2013-11-26	clk: tegra: PLLE spread spectrum control	Peter De Schrijver	1	-1/+29
2013-11-26	clk: tegra: Set the clk parent of host1x to pll_p	Andrew Chew	1	-0/+1
2013-11-26	clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks	Peter De Schrijver	2	-33/+39
2013-11-25	clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2	Mark Zhang	1	-0/+3
2013-11-25	clk: tegra: Fix vde/2d/3d clock src offset	Mark Zhang	1	-10/+3
2013-11-25	clk: tegra: Correct sbc mux width & parent	Mark Zhang	1	-6/+6