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path: root/drivers/clk/tegra
AgeCommit message (Expand)AuthorFilesLines
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler1-0/+2
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko4-1/+4
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko1-3/+3
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko8-36/+26
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver1-2/+342
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver1-0/+7
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver1-0/+14
2017-11-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds13-66/+102
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2-0/+2
2017-11-01clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen3-13/+11
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko1-5/+1
2017-11-01clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko4-0/+4
2017-11-01clk: tegra: Mark APB clock as criticalJon Hunter1-1/+1
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal1-8/+8
2017-10-19clk: tegra: Fix sor1_out clock implementationThierry Reding2-16/+47
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding4-13/+4
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding2-0/+11
2017-10-19clk: tegra: Check BPMP response return codeTimo Alho1-5/+10
2017-08-23clk: tegra: Fix Tegra210 PLLU initializationAlex Frid1-2/+4
2017-08-23clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid1-3/+3
2017-08-23clk: tegra: Fix T210 PLLRE registrationAlex Frid1-20/+1
2017-08-23clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid1-39/+9
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid4-49/+10
2017-08-23clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver1-2/+4
2017-08-23clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver1-1/+1
2017-08-23clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid1-1/+2
2017-08-23clk: tegra: Fix T210 effective NDIV calculationAlex Frid1-4/+5
2017-08-23clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver1-0/+2
2017-08-23clk: tegra210: remove non-existing VFIR clockPeter De Schrijver1-1/+0
2017-08-23clk: tegra: disable SSC for PLL_D2Peter De Schrijver1-1/+1
2017-08-23clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver1-1/+1
2017-08-23clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver1-20/+24
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring1-7/+5
2017-04-04clk: tegra: Don't reset PLL-CX if it is already enabledJon Hunter1-4/+4
2017-04-04clk: tegra: Add missing Tegra210 clocksPeter De Schrijver3-0/+19
2017-04-04clk: tegra: Propagate clk_out_x rate to parentAlex Frid1-2/+4
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding2-2/+2
2017-03-20clk: tegra: Mark TEGRA210_CLK_DBGAPB as always onPeter De Schrijver1-0/+2
2017-03-20clk: tegra: Add SATA seq input controlPeter De Schrijver1-0/+25
2017-03-20clk: tegra: Add Tegra210 special resetsPeter De Schrijver1-0/+85
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver2-197/+272
2017-03-20clk: tegra: Implement reset control resetMikko Perttunen1-0/+16
2017-03-20clk: tegra: Fix disable unused for clocks sharing enable bitPeter De Schrijver1-0/+3
2017-03-20clk: tegra: Handle UTMIPLL IDDQPeter De Schrijver1-0/+26
2017-03-20clk: tegra: Add aclkPeter De Schrijver1-0/+10
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver2-5/+89