linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2018-12-14	clk: tegra: Fix maximum audio sync clock for Tegra124/210	Jon Hunter	1	-2/+2
2018-07-25	clk: tegra: Add sdmmc mux divider clock	Peter De-Schrijver	1	-0/+26
2018-07-25	clk: tegra: Refactor fractional divider calculation	Peter De Schrijver	1	-0/+3
2018-07-25	clk: tegra: Fix includes required by fence_udelay()	Aapo Vienamo	1	-0/+1
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko	1	-1/+1
2018-03-08	clk: tegra: add fence_delay for clock registers	Peter De Schrijver	1	-0/+7
2017-10-19	clk: tegra: Add peripheral clock registration helper	Thierry Reding	1	-0/+3
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	1	-6/+0
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	1	-1/+1
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver	1	-1/+6
2017-03-20	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver	1	-2/+2
2017-03-20	clk: tegra: Fix type for m field	Peter De Schrijver	1	-1/+1
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	1	-0/+17
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	1	-0/+6
2016-04-28	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding	1	-0/+17
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding	1	-2/+2
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	1	-0/+3
2015-12-17	clk: tegra: Add Super Gen5 Logic	Bill Huang	1	-0/+3
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang	1	-0/+4
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein	1	-0/+4
2015-12-17	clk: tegra: pll: Add Set_default logic	Bill Huang	1	-0/+11
2015-12-17	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang	1	-0/+4
2015-12-17	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein	1	-0/+9
2015-12-17	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein	1	-0/+24
2015-11-20	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang	1	-0/+4
2015-11-20	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein	1	-0/+13
2015-11-20	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein	1	-1/+14
2015-11-20	clk: tegra: pll: Change misc_reg count from 3 to 6	Bill Huang	1	-1/+3
2015-11-20	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein	1	-0/+1
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-1/+1
2015-10-20	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein	1	-1/+17
2015-10-20	clk: tegra: Update struct tegra_clk_pll_params kerneldoc	Thierry Reding	1	-3/+15
2015-10-20	clk: tegra: Fix comments for structure definitions	Rhyland Klein	1	-37/+37
2015-07-16	clk: tegra: Introduce ability for SoC-specific reset control callbacks	Mikko Perttunen	1	-0/+3
2015-05-13	clk: tegra: EMC clock driver depends on EMC driver	Thierry Reding	1	-0/+9
2015-05-13	clk: tegra: Add EMC clock driver	Mikko Perttunen	1	-0/+3
2015-04-10	clk: tegra: Model oscillator as clock	Thierry Reding	1	-4/+4
2015-04-10	clk: tegra: Fix typo tabel -> table	Thierry Reding	1	-1/+1
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding	1	-0/+2
2013-12-11	clk: tegra: remove legacy reset APIs	Stephen Warren	1	-1/+0
2013-12-11	clk: tegra: implement a reset driver	Stephen Warren	1	-1/+1
2013-11-26	clk: tegra: add TEGRA_PERIPH_NO_GATE	Peter De Schrijver	1	-0/+1
2013-11-26	clk: tegra: add locking to periph clks	Peter De Schrijver	1	-4/+6
2013-11-26	clk: tegra: Add support for PLLSS	Peter De Schrijver	1	-0/+5
2013-11-26	clk: tegra: introduce common gen4 super clock	Peter De Schrijver	1	-0/+3
2013-11-26	clk: tegra: move PMC, fixed clocks to common files	Peter De Schrijver	1	-0/+7
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	1	-2/+9
2013-11-26	clk: tegra: move audio clk to common file	Peter De Schrijver	1	-0/+4
2013-11-26	clk: tegra: add clkdev registration infra	Peter De Schrijver	1	-0/+7
2013-11-26	clk: tegra: add common infra for DT clocks	Peter De Schrijver	1	-0/+7