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path: root/drivers/clk/tegra/clk-tegra30.c
AgeCommit message (Expand)AuthorFilesLines
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko1-2/+4
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni1-3/+2
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni1-15/+3
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni1-4/+0
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni1-0/+2
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni1-0/+4
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko1-1/+1
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko1-2/+0
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko1-9/+16
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko1-11/+27
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2018-12-14clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter1-3/+3
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter1-1/+8
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+1
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko1-0/+1
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-10/+4
2017-11-01clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko1-0/+1
2017-10-19clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal1-8/+8
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding1-3/+1
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver1-0/+1
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-111/+2
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach1-0/+1
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang1-1/+1
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-110/+117
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-9/+15
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-1/+1
2015-11-18clk: tegra: Format tables consistentlyThierry Reding1-189/+189
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-10/+5
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding1-1/+1
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein1-1/+7
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
2015-05-13clk: tegra: Fix hda2codec_2x clock name for Tegra30Marcel Ziswiler1-1/+1
2015-04-10clk: tegra: Model oscillator as clockThierry Reding1-1/+2
2015-04-10clk: tegra: Use consistent indentationThierry Reding1-10/+10
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+6
2014-07-17ARM: tegra: Convert PMC to a driverThierry Reding1-1/+1
2014-07-17ARM: tegra: Move includes to include/soc/tegraThierry Reding1-1/+4
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren1-7/+0
2013-12-11clk: tegra: implement a reset driverStephen Warren1-1/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot1-1/+1
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding1-1/+3
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding1-0/+1
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver1-895/+403
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-2/+2
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver1-27/+35
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver1-28/+11
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver1-201/+116
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver1-9/+10