summaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra/clk-tegra20.c
AgeCommit message (Expand)AuthorFilesLines
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko1-2/+5
2020-03-12clk: tegra: Remove audio clocks configuration from clock driverSowjanya Komatineni1-3/+2
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni1-4/+0
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko1-1/+1
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko1-2/+0
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko1-9/+16
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko1-41/+14
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2018-11-08clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko1-0/+10
2018-11-08clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko1-10/+26
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko1-1/+31
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko1-4/+2
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko1-0/+14
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko1-0/+1
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko1-3/+3
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko1-13/+10
2017-11-01clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko1-1/+1
2017-11-01clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko1-5/+1
2017-11-01clk: tegra: Add AHB DMA clock entryDmitry Osipenko1-0/+1
2017-10-19clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding1-3/+1
2016-04-28treewide: Fix typos in printkMasanari Iida1-1/+1
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd1-6/+4
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-72/+78
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-8/+10
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-1/+1
2015-11-18clk: tegra: Format tables consistentlyThierry Reding1-143/+134
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-3/+2
2015-07-20clk: tegra: Properly include clk.hStephen Boyd1-1/+0
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding1-1/+7
2014-02-17clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver1-0/+2
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren1-6/+0
2013-12-11clk: tegra: implement a reset driverStephen Warren1-1/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot1-0/+1
2013-11-26clk: tegra: move tegra20 to common infraPeter De Schrijver1-402/+255
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver1-2/+2
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver1-17/+27
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver1-27/+9
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver1-138/+82
2013-08-19clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan1-2/+4
2013-08-08clk: tegra20: Fix incorrect placement of __initdataSachin Kamat1-1/+1
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad1-1/+2
2013-05-20clk: tegra: add ac97 controller clockLucas Stach1-0/+8
2013-05-20clk: tegra: remove USB from clk init tableLucas Stach1-3/+0
2013-05-04Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-85/+99
2013-05-02Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds1-34/+2
2013-04-09Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel...Arnd Bergmann1-34/+2
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver1-1/+1
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver1-10/+10
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver1-0/+7
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver1-72/+72