Age | Commit message (Expand) | Author | Files | Lines |
2021-01-05 | memory: tegra124-emc: Make driver modular | Dmitry Osipenko | 1 | -3/+23 |
2020-05-12 | clk: tegra: Fix initial rate for pll_a on Tegra124 | Thierry Reding | 1 | -1/+1 |
2020-03-12 | clk: tegra: Remove audio clocks configuration from clock driver | Sowjanya Komatineni | 1 | -3/+2 |
2020-03-12 | clk: tegra: Remove tegra_pmc_clk_init along with clk ids | Sowjanya Komatineni | 1 | -23/+10 |
2020-03-12 | clk: tegra: Remove CLK_M_DIV fixed clocks | Sowjanya Komatineni | 1 | -4/+0 |
2020-03-12 | clk: tegra: Add Tegra OSC to clock lookup | Sowjanya Komatineni | 1 | -0/+2 |
2020-03-12 | clk: tegra: Add support for OSC_DIV fixed clocks | Sowjanya Komatineni | 1 | -0/+4 |
2019-11-11 | clk: tegra: Reimplement SOR clock on Tegra124 | Thierry Reding | 1 | -9/+13 |
2019-11-11 | clk: tegra: Rename sor0_lvds to sor0_out | Thierry Reding | 1 | -6/+6 |
2019-11-11 | clk: tegra: Move SOR0 implementation to Tegra124 | Thierry Reding | 1 | -0/+49 |
2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner | 1 | -12/+1 |
2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd | 1 | -2/+1 |
2019-04-25 | clk: tegra124: Remove lock-enable bit from PLLM | Dmitry Osipenko | 1 | -2/+1 |
2019-04-23 | clk: core: replace clk_{readl,writel} with {readl,writel} | Jonas Gorski | 1 | -2/+2 |
2018-12-14 | clk: tegra: Fix maximum audio sync clock for Tegra124/210 | Jon Hunter | 1 | -1/+8 |
2018-07-08 | clk: tegra: Make vde a child of pll_c3 | Thierry Reding | 1 | -1/+1 |
2018-07-08 | clk: tegra: Make vic03 a child of pll_c3 | Thierry Reding | 1 | -0/+1 |
2018-05-18 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 | Dmitry Osipenko | 1 | -1/+1 |
2018-03-12 | clk: tegra: Specify VDE clock rate | Dmitry Osipenko | 1 | -1/+1 |
2018-03-12 | clk: tegra: Mark HCLK, SCLK and EMC as critical | Dmitry Osipenko | 1 | -4/+3 |
2017-03-20 | clk: tegra: Add CEC clock | Peter De Schrijver | 1 | -0/+1 |
2016-06-30 | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker | 1 | -154/+2 |
2016-04-28 | clk: tegra: dpaux and dpaux1 are fixed factor clocks | Thierry Reding | 1 | -0/+4 |
2015-11-20 | clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate | Rhyland Klein | 1 | -30/+63 |
2015-11-20 | clk: tegra: pll: Don't unconditionally set LOCK flags | Rhyland Klein | 1 | -9/+15 |
2015-11-20 | clk: tegra: Constify pdiv-to-hw mappings | Thierry Reding | 1 | -5/+5 |
2015-11-18 | clk: tegra: Format tables consistently | Thierry Reding | 1 | -184/+186 |
2015-11-18 | clk: tegra: Miscellaneous coding style cleanups | Thierry Reding | 1 | -3/+3 |
2015-11-18 | clk: tegra: Fix 26 MHz oscillator frequency | Thierry Reding | 1 | -1/+1 |
2015-10-20 | clk: tegra: Modify tegra_audio_clk_init to accept more plls | Rhyland Klein | 1 | -1/+7 |
2015-08-25 | clk: tegra: Fix some static checker problems | Stephen Boyd | 1 | -4/+4 |
2015-08-25 | Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Stephen Boyd | 1 | -0/+82 |
2015-07-20 | clk: tegra: Properly include clk.h | Stephen Boyd | 1 | -1/+0 |
2015-07-16 | clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend | Tuomas Tynkkynen | 1 | -0/+14 |
2015-07-16 | clk: tegra: Add DFLL DVCO reset control for Tegra124 | Paul Walmsley | 1 | -0/+68 |
2015-05-13 | clk: tegra: Set the EMC clock as the parent of the MC clock | Tomeu Vizoso | 1 | -12/+1 |
2015-05-13 | clk: tegra: Add EMC clock driver | Mikko Perttunen | 1 | -1/+4 |
2015-05-13 | clk: tegra: Remove old Tegra124 EMC clock | Mikko Perttunen | 1 | -1/+0 |
2015-04-10 | clk: tegra: Use the proper parent for plld_dsi | Thierry Reding | 1 | -6/+8 |
2015-04-10 | clk: tegra: Model oscillator as clock | Thierry Reding | 1 | -1/+2 |
2015-04-10 | clk: tegra: Enable HDA to HDMI clocks on Tegra124 | Dylan Reid | 1 | -0/+5 |
2015-02-02 | clk: tegra: Define PLLD_DSI and remove dsia(b)_mux | Mark Zhang | 1 | -20/+16 |
2015-02-02 | clk: tegra: Add support for the Tegra132 CAR IP block | Paul Walmsley | 1 | -9/+121 |
2015-02-02 | clk: tegra124: Add init data for dsi lp clocks | Sean Paul | 1 | -0/+2 |
2014-11-26 | clk: tegra: Implement memory-controller clock | Thierry Reding | 1 | -1/+6 |
2014-09-18 | clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks | Mikko Perttunen | 1 | -0/+8 |
2014-06-27 | clk: tegra124: init table updates | Peter De Schrijver | 1 | -0/+6 |
2014-06-25 | clk: tegra: Add SATA clocks to Tegra124 initialization table | Mikko Perttunen | 1 | -0/+2 |
2014-06-25 | clk: tegra: fix vi_sensor clocks on Tegra124 | Peter De Schrijver | 1 | -1/+1 |
2014-05-22 | clk: tegra: Initialize xusb clocks | Andrew Bresticker | 1 | -0/+6 |