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path: root/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
AgeCommit message (Expand)AuthorFilesLines
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni1-0/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-10/+1
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann1-16/+504
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo1-0/+426
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo1-5/+44
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver1-11/+34
2019-01-09clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter1-1/+3
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen1-7/+5
2016-11-10clk: tegra: dfll: Use builtin_platform_driver to simplify the codeWei Yongjun1-6/+1
2016-11-04clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modularPaul Gortmaker1-14/+2
2016-04-28clk: tegra: dfll: Reformat CVB frequency tableThierry Reding1-25/+25
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding1-4/+27
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding1-6/+5
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding1-14/+9
2015-07-16clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen1-0/+166