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path: root/drivers/clk/tegra/clk-dfll.h
AgeCommit message (Expand)AuthorFilesLines
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni1-0/+2
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo1-1/+5
2017-11-01clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen1-1/+1
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding1-0/+2
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding1-8/+2
2016-04-28clk: tegra: dfll: Update kerneldocThierry Reding1-5/+5
2015-07-16clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen1-1/+1
2015-07-16clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen1-0/+54