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path: root/drivers/clk/sunxi-ng
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2017-05-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds17-53/+710
2017-04-28clk: sunxi-ng: always select CCU_GATEArnd Bergmann1-1/+1
2017-04-21Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd7-18/+17
2017-04-19Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd13-37/+695
2017-04-13clk: sunxi-ng: a80: Fix audio PLL comment not matching actual codeChen-Yu Tsai1-2/+1
2017-04-13clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatchChen-Yu Tsai2-3/+3
2017-04-13clk: sunxi-ng: use 1 as fallback for minimum multiplierChen-Yu Tsai4-11/+11
2017-04-13clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
2017-04-13clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocksChen-Yu Tsai2-0/+61
2017-04-13clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driverTobias Regnery1-0/+1
2017-04-13clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERTobias Regnery1-0/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU CLK_NUMBER valueIcenowy Zheng1-1/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU ir clk parentIcenowy Zheng1-1/+1
2017-04-06clk: sunxi-ng: Display index when clock registration failsPriit Laes1-2/+2
2017-04-05clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorChen-Yu Tsai1-7/+11
2017-04-05clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocksChen-Yu Tsai1-18/+52
2017-04-05clk: sunxi-ng: mult: Support PLL lock detectionChen-Yu Tsai2-0/+4
2017-04-04clk: sunxi-ng: add support for PRCM CCUsIcenowy Zheng4-0/+247
2017-03-20clk: sunxi-ng: fix recalc_rate formula of NKMP clocksIcenowy Zheng1-1/+1
2017-03-20clk: sunxi-ng: Fix div/mult settings for osc12M on A64Philipp Tomsich1-1/+1
2017-03-06clk: sunxi-ng: sun5i: Fix mux width for csi clockPriit Laes1-1/+1
2017-03-06clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCsPeter Robinson1-0/+8
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng3-9/+323
2017-03-06clk: sunxi-ng: gate: Support common pre-dividersChen-Yu Tsai1-0/+47
2017-03-06clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai1-1/+1
2017-03-06clk: sunxi: ccu-sun5i needs nkmpArnd Bergmann1-0/+1
2017-03-06clk: sunxi-ng: mp: Adjust parent rate for pre-dividersChen-Yu Tsai1-0/+8
2017-02-06clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()Wei Yongjun1-1/+1
2017-02-06clk: sunxi-ng: select SUNXI_CCU_MULT for sun5iArnd Bergmann1-0/+1
2017-02-06clk: sunxi-ng: Check kzalloc() for errors and cleanup error pathStephen Boyd1-0/+15
2017-01-30clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai3-0/+317
2017-01-30clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai3-0/+170
2017-01-30clk: sunxi-ng: Add A80 CCUChen-Yu Tsai4-0/+1291
2017-01-30clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2-2/+9
2017-01-30clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai1-1/+12
2017-01-30clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai1-0/+15
2017-01-30clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai1-3/+4
2017-01-27clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard1-1/+1
2017-01-27clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard1-0/+12
2017-01-23clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard4-0/+1100
2017-01-23clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2-1/+9
2017-01-23clk: sunxi-ng: Implement multiplier maximumMaxime Ripard6-20/+32
2017-01-23clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard1-1/+1
2017-01-23clk: sunxi-ng: Implement factors offsetsMaxime Ripard8-29/+79
2017-01-23clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2-0/+10
2017-01-20clk: sunxi-ng: add support for V3s CCUIcenowy Zheng4-0/+666
2017-01-17clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand1-1/+1
2017-01-02clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper1-2/+2
2017-01-02clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng1-1/+1
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng1-0/+10