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path:
root
/
drivers
/
clk
/
sunxi-ng
/
ccu-sun8i-h3.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-08-04
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
Icenowy Zheng
1
-1
/
+1
2017-08-04
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
Chen-Yu Tsai
1
-0
/
+11
2017-06-07
clk: sunxi-ng: Support multiple variable pre-dividers
Chen-Yu Tsai
1
-5
/
+5
2017-03-06
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
Icenowy Zheng
1
-7
/
+320
2017-01-02
clk: sunxi-ng: fix PLL_CPUX adjusting on H3
Ondrej Jirman
1
-0
/
+10
2016-11-11
clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
Chen-Yu Tsai
1
-5
/
+5
2016-09-14
Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...
Stephen Boyd
1
-5
/
+5
2016-08-29
clk: sunxi-ng: Fix wrong reset register offsets
Jorik Jonker
1
-8
/
+8
2016-08-25
clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
Chen-Yu Tsai
1
-5
/
+5
2016-07-11
clk: sunxi-ng: h3: Fix audio clock divider offset
Maxime Ripard
1
-2
/
+2
2016-07-08
clk: sunxi-ng: Add H3 clocks
Maxime Ripard
1
-0
/
+826