linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2018-12-04	clk: sunxi-ng: h3: Allow parent change for ve clock	Jernej Skrabec	1	-1/+1
2018-12-03	clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent	Chen-Yu Tsai	1	-1/+1
2018-08-27	clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video	Jernej Skrabec	1	-12/+13
2018-03-02	clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate	Jernej Skrabec	1	-3/+6
2018-03-02	clk: sunxi-ng: h3: h5: Add minimal rate for video PLL	Jernej Skrabec	1	-11/+12
2017-10-13	clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-13/+25
2017-09-17	clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock	Icenowy Zheng	1	-1/+1
2017-09-17	clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs	Icenowy Zheng	1	-9/+9
2017-08-23	Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...	Stephen Boyd	1	-1/+12
2017-08-04	clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3	Icenowy Zheng	1	-1/+1
2017-08-04	clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change	Chen-Yu Tsai	1	-0/+11
2017-07-21	clk: Convert to using %pOF instead of full_name	Rob Herring	1	-2/+1
2017-06-07	clk: sunxi-ng: Support multiple variable pre-dividers	Chen-Yu Tsai	1	-5/+5
2017-03-06	clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver	Icenowy Zheng	1	-7/+320
2017-01-02	clk: sunxi-ng: fix PLL_CPUX adjusting on H3	Ondrej Jirman	1	-0/+10
2016-11-11	clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks	Chen-Yu Tsai	1	-5/+5
2016-09-14	Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...	Stephen Boyd	1	-5/+5
2016-08-29	clk: sunxi-ng: Fix wrong reset register offsets	Jorik Jonker	1	-8/+8
2016-08-25	clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents	Chen-Yu Tsai	1	-5/+5
2016-07-11	clk: sunxi-ng: h3: Fix audio clock divider offset	Maxime Ripard	1	-2/+2
2016-07-08	clk: sunxi-ng: Add H3 clocks	Maxime Ripard	1	-0/+826