linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2018-05-15	clk: socfpga: stratix10: suppress unbinding platform's clock driver	Dinh Nguyen	1	-0/+1
2018-05-15	clk: socfpga: stratix10: use platform driver APIs	Dinh Nguyen	1	-22/+17
2018-04-06	clk: socfpga: stratix10: add clock driver for Stratix10 platform	Dinh Nguyen	7	-5/+853
2017-11-02	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	Greg Kroah-Hartman	1	-0/+1
2017-06-19	clk: socfpga: Fix the smplsel on Arria10 and Stratix10	Dinh Nguyen	2	-1/+4
2016-02-22	clk: socfpga: allow for multiple parents on Arria10 periph clocks	Dinh Nguyen	2	-9/+4
2016-02-08	clk: socfpga: fix __init annotation	Arnd Bergmann	1	-1/+1
2015-08-24	clk: socfpga: Add a second parent option for the dbg_base_clk	Dinh Nguyen	2	-4/+15
2015-07-28	clk: socfpga: switch to GENMASK()	Andy Shevchenko	5	-5/+4
2015-07-20	clk: socfpga: Remove clk.h and clkdev.h includes	Stephen Boyd	7	-7/+6
2015-06-09	clk: socfpga: remove a stray tab	Dan Carpenter	1	-1/+1
2015-06-05	clk: socfpga: make use of of_clk_parent_fill helper function	Dinh Nguyen	2	-11/+2
2015-05-21	clk: socfpga: add a clock driver for the Arria 10 platform	Dinh Nguyen	6	-1/+469
2015-05-21	clk: socfpga: update clk.h so for Arria10 platform to use	Dinh Nguyen	2	-5/+5
2015-05-14	clk: socfpga: Silence sparse warning	Stephen Boyd	1	-1/+1
2015-05-14	clk: socfpga: Silence sparse warning	Stephen Boyd	1	-1/+1
2014-05-12	Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...	Mike Turquette	3	-4/+23
2014-05-12	clk: socfpga: add divider registers to the main pll outputs	Dinh Nguyen	3	-4/+23
2014-04-30	clk: socfpga: fix clock driver for 3.15	Dinh Nguyen	2	-20/+10
2014-03-18	clk: socfpga: Fix section mismatch warning	Dinh Nguyen	1	-1/+1
2014-02-26	clk: socfpga: Support multiple parents for the pll clocks	Dinh Nguyen	1	-4/+22
2014-02-26	clk: socfpga: Fix integer overflow in clock calculation	Dinh Nguyen	1	-3/+5
2014-02-18	clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"	Dinh Nguyen	1	-0/+68
2014-02-18	clk: socfpga: split clk code	Steffen Trumtrar	6	-306/+462
2014-02-18	clk: socfpga: fix define typo	Steffen Trumtrar	1	-3/+3
2014-02-18	clk: socfpga: remove unused field	Steffen Trumtrar	1	-1/+0
2014-02-18	clk: socfpga: Remove socfpga_init_clocks	Dinh Nguyen	1	-10/+0
2014-02-18	clk: socfpga: Look for the GPIO_DB_CLK by its offset	Dinh Nguyen	1	-2/+3
2014-02-18	clk: socfpga: Map the clk manager base address in the clock driver	Dinh Nguyen	1	-4/+16
2013-12-19	clk: socfpga: Use NULL instead of 0	Sachin Kamat	1	-1/+1
2013-11-27	clk: socfpga: Remove check for "reg" property in socfpga_clk_init	Dinh Nguyen	1	-3/+1
2013-10-07	clk: socfpga: Fix incorrect sdmmc clock name	Dinh Nguyen	1	-1/+1
2013-06-11	ARM: socfpga: Add support to gate peripheral clocks	Dinh Nguyen	1	-9/+185
2013-04-14	ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries	Dinh Nguyen	1	-21/+142
2012-07-19	ARM: socfpga: initial support for Altera's SOCFPGA platform	Dinh Nguyen	2	-0/+52