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path: root/drivers/clk/socfpga/clk.h
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2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner1-10/+1
2018-04-06clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen1-0/+4
2017-06-19clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen1-0/+3
2015-08-24clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen1-0/+1
2015-07-28clk: socfpga: switch to GENMASK()Andy Shevchenko1-1/+0
2015-07-20clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd1-1/+0
2015-05-21clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen1-0/+5
2015-05-21clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen1-1/+5
2014-05-12clk: socfpga: add divider registers to the main pll outputsDinh Nguyen1-0/+4
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar1-0/+57