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path:
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/
drivers
/
clk
/
renesas
/
r9a07g044-cpg.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-10-08
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Biju Das
1
-0
/
+36
2021-10-08
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...
Lad Prabhakar
1
-0
/
+18
2021-09-24
clk: renesas: r9a07g044: Add GbEthernet clock/reset
Biju Das
1
-0
/
+10
2021-09-24
clk: renesas: r9a07g044: Add ethernet clock sources
Biju Das
1
-1
/
+18
2021-09-24
clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
Biju Das
1
-0
/
+2
2021-07-26
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
Lad Prabhakar
1
-1
/
+2
2021-07-19
clk: renesas: r9a07g044: Add clock and reset entries for ADC
Lad Prabhakar
1
-0
/
+6
2021-07-19
clk: renesas: r9a07g044: Add clock and reset entries for CANFD
Lad Prabhakar
1
-0
/
+4
2021-07-19
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
Geert Uytterhoeven
1
-1
/
+1
2021-07-19
clk: renesas: r9a07g044: Add GPIO clock and reset entries
Lad Prabhakar
1
-0
/
+5
2021-07-19
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
Biju Das
1
-0
/
+20
2021-07-19
clk: renesas: r9a07g044: Add USB clocks/resets
Biju Das
1
-0
/
+12
2021-07-19
clk: renesas: r9a07g044: Add DMAC clocks/resets
Biju Das
1
-0
/
+8
2021-07-19
clk: renesas: r9a07g044: Add I2C clocks/resets
Biju Das
1
-0
/
+12
2021-07-12
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
Biju Das
1
-26
/
+36
2021-07-12
clk: renesas: r9a07g044: Add P2 Clock support
Biju Das
1
-0
/
+4
2021-07-12
clk: renesas: r9a07g044: Fix P1 Clock
Biju Das
1
-3
/
+3
2021-07-12
clk: renesas: r9a07g044: Rename divider table
Biju Das
1
-3
/
+4
2021-06-10
clk: renesas: Add support for R9A07G044 SoC
Lad Prabhakar
1
-0
/
+127