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path: root/drivers/clk/renesas/r9a07g044-cpg.c
AgeCommit message (Expand)AuthorFilesLines
2021-10-08clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das1-0/+36
2021-10-08clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar1-0/+18
2021-09-24clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das1-0/+10
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das1-1/+18
2021-09-24clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das1-0/+2
2021-07-26clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar1-1/+2
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar1-0/+6
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar1-0/+4
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven1-1/+1
2021-07-19clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar1-0/+5
2021-07-19clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2021-07-19clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das1-0/+12
2021-07-19clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das1-0/+8
2021-07-19clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das1-0/+12
2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das1-26/+36
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das1-0/+4
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das1-3/+3
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das1-3/+4
2021-06-10clk: renesas: Add support for R9A07G044 SoCLad Prabhakar1-0/+127