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path: root/drivers/clk/renesas/r8a779g0-cpg-mssr.c
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2022-11-15clk: renesas: r8a779g0: Add Z0 clock supportGeert Uytterhoeven1-0/+1
Add support for the Z0 (Cortex-A76 Sub-System) clock on R-Car V4H, based on the existing support for Z clocks on R-Car Gen4. Extracted from a patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/75daa1fd8fa7eaef7b8945bb5906c787222c7ac4.1668423063.git.geert+renesas@glider.be
2022-11-08clk: renesas: r8a779g0: Add CMT clocksWolfram Sang1-0/+4
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221104151135.4706-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08clk: renesas: r8a779g0: Add TMU and SASYNCRT clocksWolfram Sang1-0/+6
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221103205546.24836-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-26clk: renesas: r8a779g0: Add RPC-IF clockGeert Uytterhoeven1-1/+2
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF) on the Renesas R-Car V4H (R8A779G0) SoC. While at it, fix table alignment in the definition of the related RPCSRC internal clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/f0609c82e742865be753b67a0a6080f193f405ad.1665583328.git.geert+renesas@glider.be
2022-10-26clk: renesas: r8a779g0: Add SDHI clocksGeert Uytterhoeven1-1/+3
Add the SD0H core clock and the SDHI module clock, which are used by the SD Card/MMC Interface on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/e9b05d102160cc3f7395ac53a533e81c07307d5e.1665558175.git.geert+renesas@glider.be
2022-10-26clk: renesas: r8a779g0: Add TPU clockGeert Uytterhoeven1-0/+1
Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/f2c1e2c5411b7bd6af726e6baf6e1efc354a7cdf.1665147497.git.geert+renesas@glider.be
2022-10-26clk: renesas: r8a779g0: Add PWM clockGeert Uytterhoeven1-0/+1
Add the module clock used by the PWM timers on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/a33d0e51c2fe8a0e6c89f3fd92db7c4bf5c33074.1665147497.git.geert+renesas@glider.be
2022-10-26clk: renesas: r8a779g0: Add SCIF clocksGeert Uytterhoeven1-0/+4
Add the module clocks used by the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/a6ab466cfdac377106494c00b811a60151cb1825.1665147497.git.geert+renesas@glider.be
2022-10-26Merge tag 'renesas-clk-fixes-for-v6.1-tag1'Geert Uytterhoeven1-4/+9
clk: renesas: Fixes for v6.1 - Correct the parent clocks for the High Speed Serial Communication Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC. Note that HSCIF0 is used for the serial console on the White-Hawk development board.
2022-10-26clk: renesas: r8a779g0: Fix HSCIF parent clocksGeert Uytterhoeven1-4/+4
As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the HSCIF modules from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/b7928abc8b9f53d5b06ec8624342f449de3d24ec.1665147497.git.geert+renesas@glider.be
2022-10-18clk: renesas: r8a779g0: Add SASYNCPER clocksGeert Uytterhoeven1-0/+5
On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or Fractional Multiplication to reduce electromagnetic interference. Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock sources for modules that must not be affected by Spread Spectrum and/or Fractional Multiplication. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be
2022-10-17clk: renesas: r8a779g0: Add INTC-EX clockGeert Uytterhoeven1-0/+1
Add the module clock used by the Interrupt Controller for External Devices (INTC-EX) aka IRQC on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8b5ab900ebce8c38604292a5138da11ad2cb072c.1664368268.git.geert+renesas@glider.be
2022-10-17clk: renesas: r8a779g0: Add MSIOF clocksGeert Uytterhoeven1-0/+6
Add the module clocks used by the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/3cb2f1798145099a46134862c6bcbdcc29ca7410.1664204336.git.geert+renesas@glider.be
2022-10-17clk: renesas: r8a779g0: Add SYS-DMAC clocksGeert Uytterhoeven1-0/+2
Add the module clocks used by the Direct Memory Access Controllers for System (SYS-DMAC) on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/d9f8322d362c7cebb29bfa7e128b4974882c4a7d.1664204336.git.geert+renesas@glider.be
2022-09-18clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven1-0/+3
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e9382b0d9acc84acc2357a6921a1459f3a32240e.1662714852.git.geert+renesas@glider.be
2022-09-18clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven1-0/+4
Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cc6a22f0ad49643e17b9921b27aa9cf0a3b8d57a.1662714852.git.geert+renesas@glider.be
2022-09-18clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven1-0/+6
Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f4b94f37950f6e976b68d0b32c324fb026d8b696.1662714852.git.geert+renesas@glider.be
2022-09-18clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven1-0/+1
Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda1-0/+218
Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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