Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-06-18 | clk: renesas: r8a77990: Add CMM clocks | Jacopo Mondi | 1 | -0/+2 |
2019-04-02 | clk: renesas: rcar-gen3: Rename DRIF clocks | Takeshi Kihara | 1 | -9/+9 |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC | Takeshi Kihara | 1 | -1/+1 |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of HS-USB | Kazuya Mizuguchi | 1 | -1/+1 |
2019-04-02 | clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI | Kazuya Mizuguchi | 1 | -1/+1 |
2019-04-02 | clk: renesas: r8a77990: Add Z2 clock | Takeshi Kihara | 1 | -0/+1 |
2018-12-04 | clk: renesas: r8a77990: Correct parent clock of DU | Takeshi Kihara | 1 | -2/+2 |
2018-09-25 | clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment | Geert Uytterhoeven | 1 | -2/+2 |
2018-08-31 | clk: renesas: r8a77990: Add missing I2C7 clock | Geert Uytterhoeven | 1 | -0/+1 |
2018-08-27 | clk: renesas: r8a77990: Correct RCLK handling | Geert Uytterhoeven | 1 | -2/+10 |
2018-05-09 | clk: renesas: cpg-mssr: Add support for R-Car E3 | Yoshihiro Shimoda | 1 | -0/+289 |