Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-06-22 | clk: renesas: rcar-gen3: Mark RWDT clocks as critical | Ulrich Hecht | 1 | -1/+1 |
2019-04-02 | clk: renesas: r8a77980: Fix RPC-IF module clock's parent | Sergei Shtylyov | 1 | -1/+1 |
2019-02-05 | clk: renesas: r8a77980: Add RPC clocks | Sergei Shtylyov | 1 | -0/+8 |
2018-09-03 | clk: renesas: r8a77980: Add CMT clocks | Sergei Shtylyov | 1 | -0/+4 |
2018-08-27 | clk: renesas: r8a77980: Add RCLK for watchdog timer | Geert Uytterhoeven | 1 | -0/+4 |
2018-08-27 | clk: renesas: r8a77980: Add OSC predivider configuration and clock | Geert Uytterhoeven | 1 | -11/+13 |
2018-04-16 | clk: renesas: r8a77980: Correct parent clock of PCIEC0 | Geert Uytterhoeven | 1 | -1/+1 |
2018-02-20 | clk: renesas: cpg-mssr: add R8A77980 support | Sergei Shtylyov | 1 | -0/+227 |