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path: root/drivers/clk/renesas/r8a7796-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2019-11-01clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportGeert Uytterhoeven1-4/+20
2019-05-21clk: renesas: r8a7796: Add CMM clocksJacopo Mondi1-0/+3
2019-05-21clk: renesas: r8a779{5|6|65}: Add TPU clockCao Van Dong1-0/+1
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara1-8/+8
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi1-1/+1
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi1-2/+2
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman1-1/+1
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman1-2/+2
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara1-2/+3
2018-12-04clk: renesas: r8a7796: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-10-18Merge branch 'clk-renesas' into clk-nextStephen Boyd1-33/+34
2018-08-30clk: renesas: use SPDX identifier for Renesas driversWolfram Sang1-4/+1
2018-08-27clk: renesas: r8a7796: Add OSC EXTAL predivider configurationGeert Uytterhoeven1-33/+33
2018-08-27clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven1-1/+2
2018-02-12clk: renesas: r8a7796: Add Z2 clockTakeshi Kihara1-0/+1
2018-02-12clk: renesas: r8a7796: Add Z clockTakeshi Kihara1-0/+1
2018-01-05clk: renesas: r8a7796: Add FDP clockABE Hiroshige1-0/+1
2017-10-16clk: renesas: r8a7796: Correct parent clock of INTC-APGeert Uytterhoeven1-1/+1
2017-08-17clk: renesas: r8a7796: Add USB3.0 clockHiromitsu Yamasaki1-0/+1
2017-08-16clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven1-17/+17
2017-05-15clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa1-0/+2
2017-05-15clk: renesas: r8a7796: Add PWM clockRyo Kodama1-0/+1
2017-05-15clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi1-0/+1
2017-05-15clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi1-0/+13
2017-05-15clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi1-0/+11
2017-05-15clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka1-0/+2
2017-03-21clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven1-1/+1
2017-03-21clk: renesas: r8a7796: Reformat core clock tableGeert Uytterhoeven1-6/+6
2017-03-21clk: renesas: r8a7796: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
2017-03-06clk: renesas: r8a7796: Add IMR clocksSergei Shtylyov1-0/+2
2017-01-27clk: renesas: r8a7796: Add IIC-DVFS clockKhiem Nguyen1-0/+1
2016-12-27clk: renesas: r8a7796: Add MSIOF controller clocksHiromitsu Yamasaki1-0/+5
2016-12-27clk: renesas: r8a7796: Add CAN FD peripheral clockChris Paterson1-0/+1
2016-12-27clk: renesas: r8a7796: Add CANFD clockChris Paterson1-0/+1
2016-12-27clk: renesas: r8a7796: Add CAN peripheral clockChris Paterson1-0/+2
2016-11-07clk: renesas: r8a7796: Add VIN clocksNiklas Söderlund1-0/+8
2016-11-07clk: renesas: r8a7796: Add CSI2 clocksNiklas Söderlund1-0/+4
2016-11-02Merge branch 'rcar-rst' into clk-renesas-for-v4.10Geert Uytterhoeven1-1/+7
2016-11-02clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven1-1/+7
2016-11-02clk: renesas: r8a7796: Add DU and LVDS clocksLaurent Pinchart1-0/+4
2016-11-02clk: renesas: r8a7796: Add VSP clocksLaurent Pinchart1-0/+5
2016-11-02clk: renesas: r8a7796: Add FCP clocksLaurent Pinchart1-0/+8
2016-11-02clk: renesas: r8a7796: Add DRIF clockRamesh Shanmugasundaram1-0/+8