Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-09-04 | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 1 | -1/+1 |
2018-10-18 | Merge branch 'clk-renesas' into clk-next | Stephen Boyd | 1 | -1/+12 |
2018-09-28 | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 1 | -4/+1 |
2018-09-19 | clk: renesas: r8a7743: Add r8a7744 support | Biju Das | 1 | -1/+12 |
2018-04-16 | clk: renesas: r8a7743: Fix LB clock divider | Geert Uytterhoeven | 1 | -1/+1 |
2018-02-20 | clk: renesas: r8a7743: Add rwdt clock | Fabrizio Castro | 1 | -0/+2 |
2016-11-10 | clk: renesas: cpg-mssr: Add R8A7743 support | Sergei Shtylyov | 1 | -0/+270 |