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path: root/drivers/clk/qcom/gcc-msm8998.c
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2022-04-19clk: qcom: gcc-msm8998: add SSC-related clocksMichael Srba1-0/+56
Add four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. If a device is known to be configured such that writing to these registers from Linux is not permitted, the 'protected-clocks' device tree property must be used to denote that fact. Signed-off-by: Michael Srba <Michael.Srba@seznam.cz> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411072156.24451-3-michael.srba@seznam.cz
2021-09-14clk: qcom: gcc-msm8998: Remove transient global "xo" clockMarijn Suijten1-27/+30
Now that all clock controllers and the DSI PLL clocks rely on "xo" being passed in DT as phandle instead of looking it up by the global "xo" name this transient clock can be removed, leaving only the fixed-factor "xo_board" clock in DT. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-4-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14clk: qcom: gcc-msm8998: Use parent_data/hws for internal clock relationsMarijn Suijten1-241/+281
Use parent_data and parent_hws to specify internal relations using pointers instead of names, and use .fw_name to retrieve external clocks from clock-names in the DT rather than the global clock tree. Note that this change relies on the "xo" and "sleep_clk" clocks to be provided in DT, as per the relevant qcom,gcc-mnsm8998.yaml dt-bindings. These clocks have been added in a prior patch [1]. [1]: https://lore.kernel.org/linux-arm-msm/20210911120101.248476-1-marijn.suijten@somainline.org/ Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-3-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-14clk: qcom: gcc-msm8998: Move parent names and mapping below GPLLsMarijn Suijten1-92/+92
Prepare for a future patch where we use .hw pointers to these GPLL clocks in the parent mapping instead of name references. This requires the GPLL clocks to be decared before parent_data arrays. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210911121340.261920-2-marijn.suijten@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno1-50/+50
All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs and not generic alphas: this was producing bad effects over the entire clock tree of MSM8998, where any GPLL child clock was declaring a false clock rate, due to their parent also showing the same. The issue resides in the calculation of the clock rate for the specific Alpha PLL type, where Fabia has a different register layout; switching the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate (calculation) reading. While at it, also make these PLLs fixed since their rate is supposed to *never* be changed while the system runs, as this would surely crash the entire SoC. Now all the children of all the PLLs are also complying with their specified clock table and system stability is improved. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as criticalAngeloGioacchino Del Regno1-0/+6
The GPU IOMMU depends on this clock and the hypervisor will crash the SoC if this clock gets disabled because the secure contexts that have been set on this IOMMU by the bootloader will become unaccessible (or they get reset). Mark this clock as critical to avoid this issue when the Adreno GPU is enabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-6-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clockAngeloGioacchino Del Regno1-0/+20
To achieve CPR-Hardened functionality this clock must be on: add it in order to be able to get it managed by the CPR3 driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-5-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clockAngeloGioacchino Del Regno1-0/+17
This clock enables the GPLL0 output to the multimedia subsystem clock controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-3-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28clk: qcom: Add missing msm8998 ufs_unipro_core_clk_srcJeffrey Hugo1-0/+27
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power savings. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23clk: qcom: Add missing msm8998 gcc_bimc_gfx_clkJeffrey Hugo1-0/+14
gcc_bimc_gfx_clk is a required clock for booting the GPU and GPU SMMU. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217164913.4783-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-07clk: qcom: Enumerate clocks and reset needed to boot the 8998 modemJeffrey Hugo1-0/+72
We need to control five additional clocks and a reset inorder to boot the modem on msm8998. If we can boot the modem, we have a place to run the wlan firmware and get wifi up and running. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191107192136.5880-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09clk: qcom: gcc: Use floor ops for SDCC clocksTaniya Das1-2/+2
Update global clock controller SDCC2/4 clocks to use the floor rcg ops, so as to use the rounded down clock rates for these clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998Marc Gonzalez1-1/+1
See similar issue solved by commit 5f2420ed2189 ("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998") Without this patch, PCIe PHY init fails: qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16 phy phy-1c06000.phy.0: phy init failed --> -16 Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22clk: qcom: Make common clk_hw registrationsJeffrey Hugo1-4/+6
Several clock controller drivers define a list of clk_hw devices, and then register those devices in probe() before using common code to process the rest of initialization. Extend the common code to accept a list of clk_hw devices to process, thus eliminating many duplicate implementations. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Suggested-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998Jeffrey Hugo1-1/+1
The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by the phy during init. The clock needs to be enabled during the init sequence, but may not be fully active until after the init sequence is complete. This causes a catch-22 if the clock status is checked during enable. As a result, skip the checks to avoid the troubling situation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09clk: qcom: Add missing freq for usb30_master_clk on 8998Jeffrey Hugo1-0/+1
The usb30_master_clk supports a 60Mhz frequency, but that is missing from the table of supported frequencies. Add it. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocksJeffrey Hugo1-0/+48
A branch clock is basically a clock that can be gated for power savings, but is also what devices/drivers consume. Configuring a branch clock's rate needs to be done at the source, so for all branch clocks which have a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on branch clocks can do what is expected. This is important as most drivers do not check the resulting clock rate after a successful clk_set_rate() call, thus the driver may get out of sync with the actual hardware state and weird issues might crop up. This has been observed with issues getting SDHCI to reliably support "fast" cards such as SDR104. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: qcom: Drop unused 8998 clockJeffrey Hugo1-14/+0
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to expect it to be needed for clients. Let's remove it because messing with the clock has been observed to cause Linux hangs when the qdss_clk is initialized by rpmcc. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: qcom: Leave mmss noc on for 8998Jeffrey Hugo1-0/+6
Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be disabled. Any mmss access depends on this clock, and its been observed that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is disabled. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-11clk: qcom: Add missing msm8998 resetsJeffrey Hugo1-0/+2
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson1-0/+75
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: gcc-msm8998: Disable halt check of UFS clocksBjorn Andersson1-3/+3
Drop the halt check of the UFS symbol clocks, in accordance with other platforms. This makes clk_disable_unused() happy and makes it possible to turn the clocks on again without an error. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_atBjorn Andersson1-28/+0
Disabling gcc_hmss_dvm_bus_clk and gcc_lpass_at_clk causes the board to lock up, and by that preventing the kernel to boot without clk_ignore_unused. gcc_hmss_dvm_bus_clk is marked always-on downstream, but not referenced, and gcc_lpass_at_clk isn't mentioned. So let's remove them until they are needed by some client. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo1-0/+87
The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05clk: qcom: Add xo dummy clk on msm8998Stephen Boyd1-0/+15
We have this dummy factor clk in place to workaround a missing rpm clk driver that can manage the XO clk state. Add it in to match what we do on msm8996. Cc: Jeffrey Hugo <jhugo@codeaurora.org> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: qcom: Fix MSM8998 resetsJeffrey Hugo1-19/+19
The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation. Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver) Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: qcom: Move frequency table macro to common fileTaniya Das1-2/+0
Frequency table macro is used by multiple clock drivers, move frequency table macro to common header file. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-16clk: qcom: Add MSM8998 Global Clock Control (GCC) driverJoonwoo Park1-0/+2834
Add support for the global clock controller found on MSM8998 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Specify regs for alpha_plls, fix white spaces and add binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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