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path: root/drivers/clk/meson/gxbb.c
AgeCommit message (Expand)AuthorFilesLines
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan1-56/+56
2017-12-08clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet1-13/+3
2017-11-27clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan1-2/+2
2017-10-20clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong1-0/+292
2017-08-23Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd1-4/+185
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet1-0/+177
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet1-3/+4
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet1-1/+2
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet1-0/+2
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet1-0/+5
2017-06-16Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ...Stephen Boyd1-5/+8
2017-06-16clk: meson: gxbb: add all clk81 parentsJerome Brunet1-5/+8
2017-06-02clk: meson-gxbb: Add const to some parent name arraysStephen Boyd1-3/+3
2017-05-29clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong1-0/+54
2017-05-29clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet1-1/+1
2017-05-29clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl1-61/+3
2017-04-07clk: meson: gxbb: add cts_i958 clockJerome Brunet1-0/+21
2017-04-07clk: meson: gxbb: add cts_mclk_i958Jerome Brunet1-0/+52
2017-04-07clk: meson: gxbb: add cts_amclkJerome Brunet1-0/+67
2017-04-07clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet1-0/+4
2017-04-04clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong1-28/+273
2017-04-04clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong1-0/+13
2017-04-04clk: meson-gxbb: Add MALI clocksNeil Armstrong1-0/+139
2017-03-27clk: meson: gxbb: mpll: use rw operationJerome Brunet1-3/+3
2017-03-27clk: meson: mpll: add rw operationJerome Brunet1-0/+30
2017-03-27clk: gxbb: put dividers and muxes in tablesJerome Brunet1-8/+20
2017-03-27clk: meson: add missing const qualifiers on gate arraysJerome Brunet1-1/+1
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl1-0/+48
2016-09-02Merge branch 'clk-meson-gxbb' into clk-nextMichael Turquette1-84/+84
2016-09-01gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller1-84/+84
2016-08-15Merge branch 'clk-meson-gxbb' into clk-nextStephen Boyd1-0/+9
2016-08-15clk: gxbb: add MMC gate clocks, and expose for DTKevin Hilman1-0/+9
2016-08-15clk: gxbb: use builtin_platform_driver to simplify the codeWei Yongjun1-5/+1
2016-07-06clk: meson: make gxbb explicitly non-modularPaul Gortmaker1-14/+4
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette1-0/+954